Renesas R5S72625 Manual De Usuario
Section 26 USB 2.0 Host/Function Module
Page 1396 of 2108
R01UH0134EJ0400 Rev. 4.00
Sep
24,
2014
SH7262 Group, SH7264 Group
Bit Bit
Name
Initial
Value R/W Description
Value R/W Description
14 BCHG 0
R/W*
1
USB Bus Change Interrupt Status
Indicates the status of the USB bus change interrupt.
0: BCHG interrupts not generated
1: BCHG interrupts generated
This module detects the BCHG interrupt when a
change in the full-speed or low-speed signal level
occurs on the USB port (a change from J-state, K-
state, or SE0 to J-state, K-state, or SE0), and sets
this bit to 1. Here, if the corresponding interrupt
enable bit has been set to 1, this module generates
the interrupt.
change in the full-speed or low-speed signal level
occurs on the USB port (a change from J-state, K-
state, or SE0 to J-state, K-state, or SE0), and sets
this bit to 1. Here, if the corresponding interrupt
enable bit has been set to 1, this module generates
the interrupt.
This module sets the LNST bits in SYSSTS0 to
indicate the current input state of the USB port.
When the BCHG interrupt is generated, repeat
reading the LNST bits until the same value is read
several times, and eliminate chattering.
indicate the current input state of the USB port.
When the BCHG interrupt is generated, repeat
reading the LNST bits until the same value is read
several times, and eliminate chattering.
A change in the USB bus state can be detected even
while the internal clock supply is stopped.
while the internal clock supply is stopped.
When the function controller function is selected, the
read value is invalid.
read value is invalid.
13
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
always be 0.