Renesas R5S72625 Manual De Usuario

 

 

Section 15   Serial Communication Interface with FIFO 

 

 

Page 728 of 2108 

 

R01UH0134EJ0400  Rev. 4.00 

 

 Sep 

24, 

2014 

SH7262 Group, SH7264 Group

4 BRK 0 R/(W)* Break Detection 

Indicates that a break signal has been detected in 
receive data. 

0: No break signal received 

[Clearing conditions] 

  BRK is cleared to 0 when the chip is a power-on 

reset 

  BRK is cleared to 0 when software reads BRK 

after it has been set to 1, then writes 0 to BRK 

1: Break signal received*

1

 

[Setting condition] 

  BRK is set to 1 when data including a framing 

error is received, and a framing error occurs with 

space 0 in the subsequent receive data 

Note:  1.  When a break is detected, transfer of the 

receive data (H'00) to SCFRDR stops 
after detection. When the break ends and 
the receive signal becomes mark 1, the 
transfer of receive data resumes.  

3 

FER 

0 

R 

Framing Error Indication 

Indicates a framing error in the data read from the 
next receive FIFO data register (SCFRDR) in 
asynchronous mode. 

0: No receive framing error occurred in the next data 

read from SCFRDR 

[Clearing conditions] 

  FER is cleared to 0 when the chip undergoes a 

power-on reset  

  FER is cleared to 0 when no framing error is 

present in the next data read from SCFRDR 

1: A receive framing error occurred in the next data 

read from SCFRDR. 

[Setting condition] 

  FER is set to 1 when a framing error is present in 

the next data read from SCFRDR