Cisco Cisco UCS B200 M2 Blade Server Hoja De Datos

Each CPU controls four memory channels, as shown in 

.

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CPU1: Channels A, B, C, and D

— Bank 1 - B0, B1; D0, D1 (blue DIMM slots)

— Bank 2 - B2, B3; D2, D3 (yellow DIMM slots)

— Bank 3 - A0, A1; C0, C1 (white DIMM slots)

— Bank 4 - A2, A3; C2, C3 (black DIMM slots)

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CPU2: Channels A, B, C, and D

— Bank 1 - B0, B1; D0, D1 (blue DIMM slots)

— Bank 2 - B2, B3; D2, D3 (yellow DIMM slots)

— Bank 3 - A0, A1; C0, C1 (white DIMM slots)

— Bank 4 - A2, A3; C2, C3 (black DIMM slots)

The DIMM and CPU physical layout is shown in 

. CPU 1 is located on the upper half of the board and 

controls the upper DIMMs. CPU 2 is located on the lower half of the board and controls the lower DIMMs.