SMSC LAN9420 Manual De Usuario

Single-Chip Ethernet Controller with HP Auto-MDIX Support and PCI Interface

SMSC LAN9420/LAN9420i

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Revision 1.22 (09-25-08)

Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of

the EEPROM, the Host must first issue the EWEN command.

If an operation is attempted, and an EEPROM device does not respond within 30mS,
LAN9420/LAN9420i will timeout, and the EPC Time-out bit (EPC_TO) in the E2P_CMD register will be
set. 

 illustrates the Host accesses required to perform an EEPROM Read or Write operation.

The Host can disable the EEPROM interface through the GPIO_CFG register. When the interface is
disabled, the EEDIO and ECLK signals can be used as general-purpose outputs, or they may be used
to monitor internal MII signals.

The EEPROM controller supports the following EEPROM operations under Host control via the
E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A
description and functional timing diagram is provided below for each operation. Please refer to the
E2P_CMD register description in 

 for E2P_CMD field settings for each command.

ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will
erase the location selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the
EEPROM does not respond within 30ms.

Idle

Write Data 

Register

Write 

Command 

Register

Read 

Command 

Register

Idle

Write 

Command 

Register

Read 

Command 

Register

Read Data 

Register

Busy Bit = 0

Busy Bit = 0