SMSC LAN9311 Manual De Usuario
Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface
Datasheet
Revision 1.4 (08-19-08)
102
SMSC LAN9311/LAN9311i
DATASHEET
8.5
Host Interface Timing
This section details the characteristics and special restrictions of the various supported host cycles.
For detailed timing specifications on supported PIO read/write operations, refer to
For detailed timing specifications on supported PIO read/write operations, refer to
. The LAN9311/LAN9311i supports the following host cycles:
Read Cycles:
(nCS or nRD controlled)
(nCS or nRD controlled)
(nCS or nRD controlled)
(nCS or nRD controlled)
Write Cycles:
(nCS or nWR controlled)
(nCS or nWR controlled)
8.5.1
Special Situations
8.5.1.1
Reset Ending During a Read Cycle
If a reset condition terminates during an active read cycle, the tail end of the read cycle will be ignored
by the LAN9311/LAN9311i.
by the LAN9311/LAN9311i.
8.5.1.2
Reset Ending Between Halves of a 16-Bit Read Pair
Some registers are readable during reset. The reset condition may terminate between halves of a 16-
bit read pair. In this case, the LAN9311/LAN9311i does not require 16-bit read to complete the DWORD
cycle. Reads to other registers during reset are not supported, and may lead to unintended behavior.
bit read pair. In this case, the LAN9311/LAN9311i does not require 16-bit read to complete the DWORD
cycle. Reads to other registers during reset are not supported, and may lead to unintended behavior.
8.5.1.3
Writes Following a Reset
Following any reset, writes from the host bus are ignored until after a read cycle is performed.
8.5.2
Special Restrictions on Back-to Back Write-Read Cycles
It is important to note that there are specific restrictions on the timing of back-to-back host write-read
operations. These restrictions concern reading the host control registers after any write cycle to the
LAN9311/LAN9311i. In some cases there is a delay between writing to the LAN9311/LAN9311i, and
the subsequent side effect (change in the control register value). For example, when writing to the TX
Data FIFO, it takes up to 135ns for the level indication to change in the
operations. These restrictions concern reading the host control registers after any write cycle to the
LAN9311/LAN9311i. In some cases there is a delay between writing to the LAN9311/LAN9311i, and
the subsequent side effect (change in the control register value). For example, when writing to the TX
Data FIFO, it takes up to 135ns for the level indication to change in the
.
In order to prevent the host from reading stale data after a write operation, minimum wait periods have
been established. These periods are specified in
been established. These periods are specified in
. The host processor is required to wait the
specified period of time after any write to the LAN9311/LAN9311i before reading the resource specified
in the table. These wait periods are for read operations that immediately follow any write cycle. Note
that the required wait period is dependant upon the register being read after the write.
in the table. These wait periods are for read operations that immediately follow any write cycle. Note
that the required wait period is dependant upon the register being read after the write.
Performing “dummy” reads of the
register is a convenient way
to guarantee that the minimum write-to-read timing restriction is met.
shows the number of
dummy reads that are required before reading the register indicated. The number of BYTE_TEST
reads in this table is based on the minimum timing for T
reads in this table is based on the minimum timing for T
cyc
(45ns). For microprocessors with slower
busses the number of reads may be reduced as long as the total time is equal to, or greater than the
time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as
long as the minimum time period is met.
time specified in the table. Note that dummy reads of the BYTE_TEST register are not required as
long as the minimum time period is met.