Intel 41210 Manual De Usuario
Intel
®
41210 Serial to Parallel PCI Bridge Developer’s Manual
45
Addressing
Instead of having a secondary IDSEL# pin, the 41210 reserves a device number of 0 for itself. The
41210 claims a Type 0 configuration transaction from PCI-X when the Upstream Configuration
Enable bit is set in the Bridge Initialization Register (
41210 claims a Type 0 configuration transaction from PCI-X when the Upstream Configuration
Enable bit is set in the Bridge Initialization Register (
) and the AD[16] signal of the transaction is asserted (HIGH) during the
address phase of the configuration transaction. The format for the Type 0 configuration cycle on
PCI-X is shown in
PCI-X is shown in
.
The 41210 ignores the device number and function number fields during Type 0 decode. The
41210 does not use the device number in the PCI-X Type 0 configuration transaction to program its
internal (primary) device number field in the PCI-X Bridge Status register.
41210 does not use the device number in the PCI-X Type 0 configuration transaction to program its
internal (primary) device number field in the PCI-X Bridge Status register.
Note:
Platforms supporting inbound Type 0 configuration cycles to the 41210 must not use address
bit[16] or bits[27:24] for IDSEL on the motherboard.
bit[16] or bits[27:24] for IDSEL on the motherboard.
5.3.3
SMBus Configuration Access
The 41210 provides a mechanism for SMBus access to its internal configuration registers. This
mechanism provides a means for server management controllers to access the registers for
debugging, and also provides a means for custom configuration of the bridge based on usage
models. See
mechanism provides a means for server management controllers to access the registers for
debugging, and also provides a means for custom configuration of the bridge based on usage
models. See
for more details.
5.4
I/O Space Access Mechanism
One I/O window can be set up in the PCI-to-PCI Bridge space for forwarding I/O transactions from
PCI Express*-to-PCI. Refer to
PCI Express*-to-PCI. Refer to
to see how I/O cycles in
the VGA range are handled. The registers and register bits listed below define the setup and control
of this I/O window:
of this I/O window:
•
I/O Base and Limit (IOBL) registers in the PCI-to-PCI Bridge configuration space
•
I/O enable bit (IOSE) in the command register in the PCI-to-PCI Bridge configuration space
To enable downstream I/O transactions, the I/O enable bit must be set in the command register in
the 41210 configuration space (bit 0 at offset 04h–05h). When the I/O enable bit is not set, all I/O
transactions initiated on PCI Express* receive a master-abort completion. The 41210 implements
one set of I/O base and limit address registers in configuration space that define an I/O address
range for the bridge. PCI Express* I/O transactions with addresses that fall inside the range defined
by the I/O base and limit registers are forwarded to PCI, and PCI I/O transactions with addresses
that fall outside this range are master-aborted.
the 41210 configuration space (bit 0 at offset 04h–05h). When the I/O enable bit is not set, all I/O
transactions initiated on PCI Express* receive a master-abort completion. The 41210 implements
one set of I/O base and limit address registers in configuration space that define an I/O address
range for the bridge. PCI Express* I/O transactions with addresses that fall inside the range defined
by the I/O base and limit registers are forwarded to PCI, and PCI I/O transactions with addresses
that fall outside this range are master-aborted.
Setting the base address to a value greater than that of the limit address turns off the I/O range.
When the I/O range is turned off, no I/O transactions are forwarded to PCI even when the I/O
enable bit is set.
When the I/O range is turned off, no I/O transactions are forwarded to PCI even when the I/O
enable bit is set.
Figure 3.
Upstream Type 0 PCI-X Configuration Cycle Address Format
B3184-01
31
26
27
28
29
30
23
24
25
19
20
21
22
15
16
17
18
12
14 13
8
9
10
11
4
5
6
7
3
2
1
0
Reserved
Type 0 Header
Dev No
00
Fnc
Ext. Add
0000000
1
Register