DLP Design Inc. 000RF2 Manual De Usuario
Rev 1.0 (January 2005)
DLP-RF2
DLP Design, Inc.
2
• Twelve I/O lines that can be configured for
digital input or output; seven lines can be
configured for analog input
configured for analog input
• Agency approvals in place for immediate
deployment in the US, Canada, and
Europe
Europe
• Default reset via shorting two jumpers at
power-up
1.0 System Overview
Using the pre-programmed SIPP firmware, the DLP-RF2 can be used in conjunction with other
DLP-RF2 and/or DLP-RF1 modules to form simple point-to-point and star configuration
systems. Both the DLP-RF1 and the DLP-RF2 can serve as host/system controllers. In the
case of the DLP-RF1, the host is a user-supplied Windows, Linux, or Mac PC that is accessed
via a USB interface and user-supplied, 6-foot USB cable. In the case of the DLP-RF2, the host
is a user-supplied microcontroller/DSP/FPGA/etc. that is accessed via a 2-wire serial interface–
TX, RX, and ground. A host processor is not necessarily required by the DLP-RF2. The SIPP
firmware within the DLP-RF2 can be accessed remotely via another transceiver and can be
used to both gain access to the MC9S08GT60’s port pins for basic digital I/O and offer a few
hardware-specific functions for measuring system power supply voltage, measuring
temperature, and controlling relays. These functions require the presence of external hardware
(purchased separately).
Using the Z-Stack ZigBee Protocol Stack from Figure 8 Wireless (licensed separately), the
DLP-RF2 can be used in conjunction with other DLP-RF1/DLP-RF2 transceivers as well as
other MC13192-based ZigBee-ready devices to form complex point-to-point, star, and mesh
networks. (For more information on creating a ZigBee-enabled system, refer to Section 2.0 on
the topic of ZigBee.)
In a system using the preprogrammed SIPP firmware, each transceiver has a unique 16-bit ID
yielding a theoretical maximum of 65,535 transceivers. Every data packet handled by the SIPP
firmware must contain, at minimum, the number of bytes in the packet, the destination
transceiver ID (packet destination), the source transceiver ID (packet origin), and a command
byte.
As shipped from DLP Design, the DLP-RF2 has an ID of 2. If more than one DLP-RF2 is to be
used in a system, then this ID must be changed to a value higher than 2. Upon reset or power
up, the ID is read from non-volatile EEPROM memory. If JP1 is shorted at power up (or before
a reset), the default ID for the DLP-RF2 is set to 2 and other transceiver settings are also
returned to a default state in the EEPROM. (Refer to Section 3.2 for additional details.)
In addition to basic packet processing and port-pin manipulation, the SIPP firmware in the
DLP-RF2 offers a Low-Power Mode designed to conserve battery power. Holding PTC1
(Header Pin 16) low at power up enables the Low-Power Mode. Once enabled, the DLP-RF2 is
in Sleep Mode until awakened by activity on digital inputs that have been enabled to wake the
processor—or by a simple preset timeout. The setup parameters for this feature are also stored
in the non-volatile EEPROM memory. If PTC1 is not held low, then the microcontroller and RF
IC remain in full power mode, offering the fastest packet processing possible. (Refer to Section
3.2 for additional details.)
DLP-RF2 and/or DLP-RF1 modules to form simple point-to-point and star configuration
systems. Both the DLP-RF1 and the DLP-RF2 can serve as host/system controllers. In the
case of the DLP-RF1, the host is a user-supplied Windows, Linux, or Mac PC that is accessed
via a USB interface and user-supplied, 6-foot USB cable. In the case of the DLP-RF2, the host
is a user-supplied microcontroller/DSP/FPGA/etc. that is accessed via a 2-wire serial interface–
TX, RX, and ground. A host processor is not necessarily required by the DLP-RF2. The SIPP
firmware within the DLP-RF2 can be accessed remotely via another transceiver and can be
used to both gain access to the MC9S08GT60’s port pins for basic digital I/O and offer a few
hardware-specific functions for measuring system power supply voltage, measuring
temperature, and controlling relays. These functions require the presence of external hardware
(purchased separately).
Using the Z-Stack ZigBee Protocol Stack from Figure 8 Wireless (licensed separately), the
DLP-RF2 can be used in conjunction with other DLP-RF1/DLP-RF2 transceivers as well as
other MC13192-based ZigBee-ready devices to form complex point-to-point, star, and mesh
networks. (For more information on creating a ZigBee-enabled system, refer to Section 2.0 on
the topic of ZigBee.)
In a system using the preprogrammed SIPP firmware, each transceiver has a unique 16-bit ID
yielding a theoretical maximum of 65,535 transceivers. Every data packet handled by the SIPP
firmware must contain, at minimum, the number of bytes in the packet, the destination
transceiver ID (packet destination), the source transceiver ID (packet origin), and a command
byte.
As shipped from DLP Design, the DLP-RF2 has an ID of 2. If more than one DLP-RF2 is to be
used in a system, then this ID must be changed to a value higher than 2. Upon reset or power
up, the ID is read from non-volatile EEPROM memory. If JP1 is shorted at power up (or before
a reset), the default ID for the DLP-RF2 is set to 2 and other transceiver settings are also
returned to a default state in the EEPROM. (Refer to Section 3.2 for additional details.)
In addition to basic packet processing and port-pin manipulation, the SIPP firmware in the
DLP-RF2 offers a Low-Power Mode designed to conserve battery power. Holding PTC1
(Header Pin 16) low at power up enables the Low-Power Mode. Once enabled, the DLP-RF2 is
in Sleep Mode until awakened by activity on digital inputs that have been enabled to wake the
processor—or by a simple preset timeout. The setup parameters for this feature are also stored
in the non-volatile EEPROM memory. If PTC1 is not held low, then the microcontroller and RF
IC remain in full power mode, offering the fastest packet processing possible. (Refer to Section
3.2 for additional details.)