Simoco EMEA Ltd SDB670AC01 Manual De Usuario
SDB670 – SERVICE MANUAL
TNM-M-E-0032
May 13
Page 37
TECHNICAL DESCRIPTION
Alignment Tool to measure the actual operating temperature and can also be used for advanced
control functions.
control functions.
5.3.4
Frequency Synthesiser
5.3.4.1
General
Refer to Figure 10 (page 42) and Figures 9, 10, 13 and 14 in TNM-S-E-0005, SDM600 Series –
Issue 4 Circuit Diagrams [2].
Issue 4 Circuit Diagrams [2].
The frequency synthesiser consists of one VCO each for the Tx and Rx, loop filter, varactor
negative bias generator, reference oscillator, a dual PLL U701, VCO buffers and PLL feedback
buffer.
negative bias generator, reference oscillator, a dual PLL U701, VCO buffers and PLL feedback
buffer.
5.3.4.2
Fractional PLL
The Fractional PLL device contains two prescalers, programmable dividers and phase
comparators to provide a main and auxiliary PLL. The main PLL of U701 controls the frequency of
the Tx/Rx VCOs via Charge Pump output CPRF at pin 1 via the Loop Filter. This voltage is set to
a nominal 1.6 V that provides a suitable operating point for the VCO varactor diodes. This voltage
will be maintained for any frequency but may vary slightly with temperature. VCO feedback to
pin 4 is provided via Feedback Buffer Q710 and associated circuitry. The auxiliary PLL is not used
in this application. The PLL operation involves the division of the 95.04 MHz reference frequency
to a preset comparator frequency of 1760 kHz (Rfr1=54) or 1728 kHz (Rfr2=55) by internal
dividers. The VCO frequency is sampled and divided down to the same comparison frequency
after which it is phase compared to the comparator reference. The fractional feature of this PLL
enables very fine increments of the channel frequency such that any customer requirement can be
fulfilled. Any error produces an offset to the Charge Pump output voltage, which is then used to
correct the VCO frequency. A valid lock detect output is derived from PLL pin 12 and is sampled
by the FPGA. During transmit, if an unlocked signal is detected, the radio will switch back to
receive mode. An unlocked signal in receive mode will cause the radio to beep. The Feedback
Buffer circuit is provided in the feedback path to provide VCO isolation and correct input level to
the PLL.
comparators to provide a main and auxiliary PLL. The main PLL of U701 controls the frequency of
the Tx/Rx VCOs via Charge Pump output CPRF at pin 1 via the Loop Filter. This voltage is set to
a nominal 1.6 V that provides a suitable operating point for the VCO varactor diodes. This voltage
will be maintained for any frequency but may vary slightly with temperature. VCO feedback to
pin 4 is provided via Feedback Buffer Q710 and associated circuitry. The auxiliary PLL is not used
in this application. The PLL operation involves the division of the 95.04 MHz reference frequency
to a preset comparator frequency of 1760 kHz (Rfr1=54) or 1728 kHz (Rfr2=55) by internal
dividers. The VCO frequency is sampled and divided down to the same comparison frequency
after which it is phase compared to the comparator reference. The fractional feature of this PLL
enables very fine increments of the channel frequency such that any customer requirement can be
fulfilled. Any error produces an offset to the Charge Pump output voltage, which is then used to
correct the VCO frequency. A valid lock detect output is derived from PLL pin 12 and is sampled
by the FPGA. During transmit, if an unlocked signal is detected, the radio will switch back to
receive mode. An unlocked signal in receive mode will cause the radio to beep. The Feedback
Buffer circuit is provided in the feedback path to provide VCO isolation and correct input level to
the PLL.
5.3.4.3
Negative Bias Generator and Loop Filter
A negative varactor bias supply similar to the front-end varactor arrangement has been used to
achieve the required broadband tuning range of the VCOs. This voltage is filtered by R706 and
C717 to provide a very clean output to the VCOs and it can vary between –0.5 V and –16 V. It is
controlled by SYN-VARSET and is derived from another PWM output from the FPGA. This voltage
is translated to a negative voltage by the circuit comprising Q701 to Q704. The resulting low noise
voltage VAR-BIAS is applied to the anode side of the VCO varactor tuning diodes as a negative
bias voltage. The –16 V rail of this supply is generated by U908A/B/F with D912 to D915 providing
the voltage multiplication needed to achieve –16 V.
achieve the required broadband tuning range of the VCOs. This voltage is filtered by R706 and
C717 to provide a very clean output to the VCOs and it can vary between –0.5 V and –16 V. It is
controlled by SYN-VARSET and is derived from another PWM output from the FPGA. This voltage
is translated to a negative voltage by the circuit comprising Q701 to Q704. The resulting low noise
voltage VAR-BIAS is applied to the anode side of the VCO varactor tuning diodes as a negative
bias voltage. The –16 V rail of this supply is generated by U908A/B/F with D912 to D915 providing
the voltage multiplication needed to achieve –16 V.
The Loop Filter, comprising R719, R719b, R721, C722 to C725a, C731d and C732, is placed in
series with CPP-RF and U701-1 and connected to VAR-BIAS as its reference. The purpose of the
Loop Filter is to remove Charge Pump reference components and other PLL generated noise.
However, this requirement conflicts with the extremely fast switching times required for DMR
operation. As a result, a quad analogue gate U700 has been added. This switches in fast time
constant values across the Loop Filter components to rapidly stabilise the CPP-RF output prior to
transmission or reception. Timing for these gates is controlled by the FPGA via SYN-FAST1 and
SYN-FAST2.
series with CPP-RF and U701-1 and connected to VAR-BIAS as its reference. The purpose of the
Loop Filter is to remove Charge Pump reference components and other PLL generated noise.
However, this requirement conflicts with the extremely fast switching times required for DMR
operation. As a result, a quad analogue gate U700 has been added. This switches in fast time
constant values across the Loop Filter components to rapidly stabilise the CPP-RF output prior to
transmission or reception. Timing for these gates is controlled by the FPGA via SYN-FAST1 and
SYN-FAST2.
5.3.4.4
Reference Oscillator
Temperature Controlled Crystal Oscillator (TCXO) U702 determines the overall frequency stability
and frequency setting of the radio. The frequency setting is achieved by adjusting its ADJ voltage
SYN-AFC1 with the Alignment Tool. In addition, the ADJ input can be used in a frequency control
loop with the demodulated I and Q signals to provide Rx Automatic Frequency Control (AFC).
and frequency setting of the radio. The frequency setting is achieved by adjusting its ADJ voltage
SYN-AFC1 with the Alignment Tool. In addition, the ADJ input can be used in a frequency control
loop with the demodulated I and Q signals to provide Rx Automatic Frequency Control (AFC).