Simoco EMEA Ltd SDB670AC01 Manual De Usuario
SDB670 – SERVICE MANUAL
TNM-M-E-0032
May 13
Page 39
TECHNICAL DESCRIPTION
U805A and U805B are set up as differential constant current amplifiers with 600 Ω source
impedances. U804A and U804B are differential voltage amplifiers with LINE-OUT source
impedances of approximately 600 Ω and 40 Ω respectively.
impedances. U804A and U804B are differential voltage amplifiers with LINE-OUT source
impedances of approximately 600 Ω and 40 Ω respectively.
An optional CODEC U800 can be provided to provide more complex functionality but is normally
not fitted.
not fitted.
5.3.5.2
Transmitter Audio
The microphone audio input signal is applied to the microphone input at S1-8 and is derived from
an external microphone unit with an applied nominal level of 40 mV
an external microphone unit with an applied nominal level of 40 mV
RMS
. This is then routed to
CODEC U803-35 as MIC-AUDIO where it is limited to approximately 800 mV
p-p
by D801.
Microphone bias, if required, is derived from U803-36, which can apply a pre-programmed bias
voltage to the microphone.
voltage to the microphone.
Alternate modulation inputs from connectors S3-4 (LINE-IN2), S5-19 (LINE-IN4), S5-14 (LINE-IN5)
can also be provided.
can also be provided.
CODEC U803 provides input switching of the audio paths after which they are fed to one of two
CODEC ADCs. The output of these is routed to the DSP via CD-OUT. All pre-emphasis, filtering,
compression and limiting processes for narrow and wideband operation are carried out in the DSP.
This processed Tx audio/data is then fed to a Modulation Equaliser that takes equalisation values
stored in flash after radio alignment. It applies these values to the Tx data and then directly
programs these into PLL U701 via its SYN-PLL-DATA/CLK/STB bus as new frequency data values
resulting in frequency modulation of the VCO. The purpose of the Modulation Equaliser is to
correct for frequency response variations caused by the VCO loop filter resulting in a flat frequency
response from 0 Hz up to the maximum modulation frequency.
CODEC ADCs. The output of these is routed to the DSP via CD-OUT. All pre-emphasis, filtering,
compression and limiting processes for narrow and wideband operation are carried out in the DSP.
This processed Tx audio/data is then fed to a Modulation Equaliser that takes equalisation values
stored in flash after radio alignment. It applies these values to the Tx data and then directly
programs these into PLL U701 via its SYN-PLL-DATA/CLK/STB bus as new frequency data values
resulting in frequency modulation of the VCO. The purpose of the Modulation Equaliser is to
correct for frequency response variations caused by the VCO loop filter resulting in a flat frequency
response from 0 Hz up to the maximum modulation frequency.
5.3.6
Power Supplies
Refer to Figure 10 (page 42) and Figures 4 and 6 in TNM-S-E-0005, SDM600 Series – Issue 4
Circuit Diagrams [2].
Circuit Diagrams [2].
5.3.6.1
Power On/Off Function
The radio ON/OFF function can be achieved in two ways as follows:
(a). Analogue control via Q902, Q922 and Q901. In this case a momentary low voltage pulse
from the control unit or microphone handset PWR ON button briefly turns on
Q902/Q922/Q901. In this time, the radio powers up and the DSP samples the PWR_DET
line after Boot Code has loaded. If this is high, it writes this status to flash, sets PWR-INH
low and gets the FPGA to set its PWR-OFF line high. This latches the radio on and the radio
remains powered up. If the DSP sees that the PWR-DET is low, it will check the ON/OFF
status in flash. If this corresponds to OFF, the DSP will power down the radio by setting
PWR-INH high. If the ON/OFF flash status corresponds to ON, the DSP sets PWR-INH low.
The FPGA will also read the ON/OFF flash status and will set its PWR-OFF line high so that
the radio will remain on.
Q902/Q922/Q901. In this time, the radio powers up and the DSP samples the PWR_DET
line after Boot Code has loaded. If this is high, it writes this status to flash, sets PWR-INH
low and gets the FPGA to set its PWR-OFF line high. This latches the radio on and the radio
remains powered up. If the DSP sees that the PWR-DET is low, it will check the ON/OFF
status in flash. If this corresponds to OFF, the DSP will power down the radio by setting
PWR-INH high. If the ON/OFF flash status corresponds to ON, the DSP sets PWR-INH low.
The FPGA will also read the ON/OFF flash status and will set its PWR-OFF line high so that
the radio will remain on.
The Power-off operation requires the ON/OFF button to be pressed for more than 2 seconds.
If the ON/OFF button is sensed going low for approximately two seconds by the DSP via the
PWR_DET line, the DSP will save radio settings to flash including the OFF status. It will then
set the PWR-INH line high, thereby turning Q901 and hence the radio off.
If the ON/OFF button is sensed going low for approximately two seconds by the DSP via the
PWR_DET line, the DSP will save radio settings to flash including the OFF status. It will then
set the PWR-INH line high, thereby turning Q901 and hence the radio off.
(b). Digital control via an external device. This is necessary when multiple devices are
connected. It enables the radio to determine which devices are connected and which one
has master control. When the ON/OFF button is pressed on any device, the radio will turn
everything on as described above and a microprocessor in any external device will note this
and send and serial ID message to the radio. After everything has been turned on, pressing
the ON/OFF button on the master will send a serial command to the radio to turn everything
has master control. When the ON/OFF button is pressed on any device, the radio will turn
everything on as described above and a microprocessor in any external device will note this
and send and serial ID message to the radio. After everything has been turned on, pressing
the ON/OFF button on the master will send a serial command to the radio to turn everything