Getac Technology Corporation V110GD Manual De Usuario

PIC32MX1XX/2XX

DS61168C

-page 42

Prelimina

2011 Microchip T

echnolo

gy Inc.

4.1.1

PERIPHERAL REGISTERS LOCATIONS

Table 4-1

through

Table 4-27

contain the peripheral address maps for the PIC32MX1XX/2XX devices.

TABLE 4-1:

BUS MATRIX REGISTER MAP

l A

F88_#)

Bit

nge

Bits

All

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

2000 BMXCON

(1)

31:16

—

BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

15:0

—

BMXWSDRM

—

BMXARB<2:0>

0041

2010 BMXDKPBA

(1)

31:16

—

0000

15:0

BMXDKPBA<15:0>

0000

2020 BMXDUDBA

(1)

31:16

—

0000

15:0

BMXDUDBA<15:0>

0000

2030 BMXDUPBA

(1)

31:16

—

0000

15:0

BMXDUPBA<15:0>

0000

2040 BMXDRMSZ

31:16

BMXDRMSZ<31:0>

xxxx

15:0

xxxx

2050 BMXPUPBA

(1)

31:16

—

BMXPUPBA<19:16>

0000

15:0

BMXPUPBA<15:0>

0000

2060 BMXPFMSZ

31:16

BMXPFMSZ<31:0>

xxxx

15:0

xxxx

2070 BMXBOOTSZ

31:16

BMXBOOTSZ<31:0>

0000

15:0

3000

Legend:

= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See

Section 11.2 “CLR, SET and INV Registers”

for more information.