Getac Technology Corporation V110GD Manual De Usuario

2011

Microchip Technology Inc.

Prelimina

1168C-p

age 55

PIC32MX1XX/2XX

3170 DCH1SSIZ

31:16

—

0000

15:0

CHSSIZ<15:0>

0000

3180 DCH1DSIZ

31:16

—

0000

15:0

CHDSIZ<15:0>

0000

3190 DCH1SPTR

31:16

—

0000

15:0

CHSPTR<15:0>

0000

31A0 DCH1DPTR

31:16

—

0000

15:0

CHDPTR<15:0>

0000

31B0 DCH1CSIZ

31:16

—

0000

15:0

CHCSIZ<15:0>

0000

31C0 DCH1CPTR

31:16

—

0000

15:0

CHCPTR<15:0>

0000

31D0 DCH1DAT

31:16

—

0000

15:0

—

CHPDAT<7:0>

0000

31E0 DCH2CON

31:16

—

0000

15:0 CHBUSY

—

CHCHNS

CHEN

CHAED

CHCHN

CHAEN

—

CHEDET

CHPRI<1:0>

0000

31F0 DCH2ECON

31:16

—

CHAIRQ<7:0>

00FF

15:0

CHSIRQ<7:0>

CFORCE CABORT

PATEN

SIRQEN

AIRQEN

—

FF00

3200 DCH2INT

31:16

—

CHSDIE

CHSHIE

CHDDIE

CHDHIE

CHBCIE

CHCCIE

CHTAIE

CHERIE 0000

15:0

—

CHSDIF

CHSHIF

CHDDIF

CHDHIF

CHBCIF

CHCCIF

CHTAIF

CHERIF 0000

3210 DCH2SSA

31:16

CHSSA<31:0>

0000

15:0

0000

3220 DCH2DSA

31:16

CHDSA<31:0>

0000

15:0

0000

3230 DCH2SSIZ

31:16

—

0000

15:0

CHSSIZ<15:0>

0000

3240 DCH2DSIZ

31:16

—

0000

15:0

CHDSIZ<15:0>

0000

3250 DCH2SPTR

31:16

—

0000

15:0

CHSPTR<15:0>

0000

3260 DCH2DPTR

31:16

—

0000

15:0

CHDPTR<15:0>

0000

3270 DCH2CSIZ

31:16

—

0000

15:0

CHCSIZ<15:0>

0000

TABLE 4-12:

DMA CHANNELS 0-3 REGISTER MAP

(1)

(CONTINUED)

irtual Addr

8_#)

gist

Name

Bit Rang

Bits

All Re

31/15

30/14

29/13

28/12

27/11

26/10

25/9

24/8

23/7

22/6

21/5

20/4

19/3

18/2

17/1

16/0

Legend:

= unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

Note 1:

All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See

Section 11.2 “CLR, SET and INV Registers”

for

more information.