Getac Technology Corporation V110GD Manual De Usuario
© 2011 Microchip Technology Inc.
Preliminary
DS61168C-page 73
PIC32MX1XX/2XX
4.2
Control Registers
through
are used for setting
the RAM and Flash memory partitions for data and
code.
code.
REGISTER 4-1:
BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit
Range
Bit
31/23/15/7
Bit
30/22/14/6
Bit
29/21/13/5
Bit
28/20/12/4
Bit
27/19/11/3
Bit
26/18/10/2
Bit
25/17/9/1
Bit
24/16/8/0
31:24
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
23:16
U-0
U-0
U-0
R/W-1
R/W-1
R/W-1
R/W-1
R/W-1
—
—
—
BMX
ERRIXI
BMX
ERRICD
BMX
ERRDMA
BMX
ERRDS
BMX
ERRIS
15:8
U-0
U-0
U-0
U-0
U-0
U-0
U-0
U-0
—
—
—
—
—
—
—
—
7:0
U-0
R/W-1
U-0
U-0
U-0
R/W-0
R/W-0
R/W-1
—
BMX
WSDRM
—
—
—
BMXARB<2:0>
Legend:
R = Readable bit
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 31-21 Unimplemented: Read as ‘0’
bit 20
bit 20
BMXERRIXI:
Enable Bus Error from IXI bit
1
= Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0
= Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19
BMXERRICD:
Enable Bus Error from ICD Debug Unit bit
1
= Enable bus error exceptions for unmapped address accesses initiated from ICD
0
= Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18
BMXERRDMA:
Bus Error from DMA bit
1
= Enable bus error exceptions for unmapped address accesses initiated from DMA
0
= Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17
BMXERRDS:
Bus Error from CPU Data Access bit (disabled in Debug mode)
1
= Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0
= Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16
BMXERRIS:
Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1
= Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0
= Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7
Unimplemented:
Read as ‘0’
bit 6
BMXWSDRM:
CPU Instruction or Data Access from Data RAM Wait State bit
1
= Data RAM accesses from CPU have one wait state for address setup
0
= Data RAM accesses from CPU have zero wait states for address setup
bit 5-3
Unimplemented:
Read as ‘0’
bit 2-0
BMXARB<2:0>:
Bus Matrix Arbitration Mode bits
111
= Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011
= Reserved (using these Configuration modes will produce undefined behavior)
010
= Arbitration Mode 2
001
= Arbitration Mode 1 (default)
000
= Arbitration Mode 0