GatesAir Inc. CZF Manual De Usuario
APEX
™
Exciter Incorporating FLO
™
Technologyr
APEX Exciter Analog Assembly Overview
Theory of Operation
26
04s40
0.fm
03/08/07
888-2604-001
Page: 4-11
WARNING: Disconnect primary power prior to servicing.
Figure 4-7 10 MHz Reference Oscillator Block Diagram
4.4.3.2
128.9 MHz IF PLL (First L. O.)
Refer to Figure 4-8, block diagram of the first local oscillator PLL. The first local oscillator
PLL generates a 128.9 MHz CW signal. It is used to convert the digitally generated 11.1
MHz 1st IF to the 140 MHz (2nd IF frequency).
PLL generates a 128.9 MHz CW signal. It is used to convert the digitally generated 11.1
MHz 1st IF to the 140 MHz (2nd IF frequency).
The 128.9 MHz output from the first local oscillator is derived from a 32 bit DDS (direct
digital synthesis) based oscillator, which is clocked at 400 MHz. The 400 MHz is generated
in a single loop PLL (phase locked loop) which is locked to the 10 MHz reference
oscillator.
digital synthesis) based oscillator, which is clocked at 400 MHz. The 400 MHz is generated
in a single loop PLL (phase locked loop) which is locked to the 10 MHz reference
oscillator.
Figure 4-8 Block Diagram First LO
J8, 10 MHz
Out, feedback
Out, feedback
J11, 10 MHz
output to 1st
and 2nd PLLs.
output to 1st
and 2nd PLLs.
U32,
3-Way
3-Way
10 MHz
OCXO
U41, Electronic
U40,
Switch
UDC Board
number, used to set the 10 MHz
FPGA Modulator board.
This board gets the 16 bit DAC
OCXO frequency, from the
used to set 16
bit DAC number.
bit DAC number.
10 kHz
Reference
Signal from
the FPGA board
Reference
Signal from
the FPGA board
U57,
U29, PLL
16 Bit DAC
Splitter
128.9 MHz to Up
Converter, +10 dBm
Converter, +10 dBm
128.9 MHz to Down
Converter, +10 dBm
Converter, +10 dBm
10 MHz
Reference
Input
Reference
Input
U31,
2-Way
2-Way
Band and
Low Pass
Filters
Low Pass
Filters
128.9 MHz
DDS
U42,
400 MHz
VCO
400 MHz
VCO
Phase
Detector
÷ N
From
Micro Controller
From
Micro Controller
U39,
U45,
Splitter