GatesAir Inc. CZF Manual De Usuario

APEX

™

 Exciter Incorporating FLO

™

 Technology

Details of the Exciter Status Screens

Navigating the LCD Display Screens

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888-2604-001

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WARNING: Disconnect primary power prior to servicing.

• 5 Vdc: This is the board input voltage, which comes from the controller board.

• 3.3 Vdc: This is the output of the 3.3 V dc to dc converter.

• 2.5 Vdc supply is derived from the 3.3 Vdc supply through an FET switch. This volt-

age is switched off if the DSP 1.8 Vdc supply faults.

• 1.8 Vdc This is the output of the 1.8 volt core power supply.

• 1.2 Vdc This is the output of the 1.2 volt core power supply.

• FPGA Temp. refers to the temperature of the FPGA board.

• GPS 5 Vdc refers to the 5 volt supply for the GPS receiver.

• FPGA cfg refers to the configuration of the FPGA, which is a microprocessor.

• FPGA prog (OK or FAULT) refers to the programing of the FPGA board.

• EEPROM: (Ok or FAULT) The EEPROM is the local board memory. It stores board 

specific information such as board revision, CPLD revision, FPGA revision, and oth-
er local data.

• PLL Unlock (OK or FAULT) Status of 11.1 MHz clock, OK represents clock locked 

to 10 MHz reference.

• FPGA Rev: Revision level of the firmware in the field programmable gate array in the 

Modulator board. 

• CPLD Rev: Revision level of the CPLD in the Modulator board.

• Board Rev: Board revision level for the Modulator board.

 ADC_DACStatus.bmp

Refer to Figure 3-11. The ADC and DAC screen entries are listed below.

• ADC Board Rev: This is the board revision for the analog to digital converter board.

• DAC Board Rev: This is the board revision for the digital to analog converter board.