Intel Pentium D 830 HH80551PG0802MN Hoja De Datos

27

 outlines the signals which include on-die termination (R

TT

). Open drain signals are also 

included. 

 provides signal reference voltages.

1.

Refer to 

 for signal descriptions.

GTL+ Common Clock 
Input

Synchronous to BCLK[1:0] BPRI#, DEFER#, RESET#, RS[2:0]#, RSP#, TRDY#,

GTL+ Common Clock I/O

Synchronous to BCLK[1:0]

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, 
DBSY#, DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, 
MCERR# 

GTL+ Source 
Synchronous I/O

Synchronous to assoc. 
strobe

2

2.

The value of A[16:3]# and A[35:17]# during the active-to-inactive edge of RESET# defines the processor
configuration options. See 

 for details.

GTL+ Strobes

Synchronous to BCLK[1:0] ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

 GTL+ Asynchronous 
Input

A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, 
LINT1/NMI, SMI#, STPCLK#

 GTL+ Asynchronous 
Output

FERR#/PBE#, IERR#, THERMTRIP#

 GTL+ Asynchronous 
Input/Output

PROCHOT#

TAP Input

Synchronous to TCK

TCK, TDI, TMS, TRST#

TAP Output

Synchronous to TCK

TDO

FSB Clock

Clock

BCLK[1:0], ITP_CLK[1:0]

3

3.

In processor systems where there is no debug port implemented on the system board, these signals are used
to support a debug port interposer. In systems with the debug port implemented on the system board, these
signals are no connects.

Power/Other

VCC, VTT, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA, 
GTLREF[1:0], COMP[1:0], COMP[3:2], IMPSEL, 
RESERVED, TESTHI[13:0], THERMDA, THERMDC, 
VCC_SENSE, VSS_SENSE, BSEL[2:0], SKTOCC#, 
DBR#

, VTTPWRGD, BOOTSELECT, PWRGOOD, 

VTT_OUT_LEFT, VTT_OUT_RIGHT, VTT_SEL, 
LL_ID[1:0], FCx, VCC_MB_REGULATION, 
VSS_MB_REGULATION, MSID[1:0], VCCPLL

REQ[4:0]#, A[16:3]#

ADSTB0#

A[35:17]#

ADSTB1#

D[15:0]#, DBI0# 

DSTBP0#, DSTBN0#

D[31:16]#, DBI1# 

DSTBP1#, DSTBN1#

D[47:32]#, DBI2# 

DSTBP2#, DSTBN2#

D[63:48]#, DBI3# 

DSTBP3#, DSTBN3#