Intel Pentium D 830 HH80551PG0802MN Hoja De Datos
Los códigos de productos
HH80551PG0802MN
30
Datasheet
Electrical Specifications
Table 2-12. PWRGOOD Input and TAP Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1, 2
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All outputs are open drain.
V
HYS
Input Hysteresis
200
350
mV
3
3.
V
HYS
represents the amount of hysteresis, nominally centered about 0.5 * V
TT
, for all TAP inputs.
V
T
+
Input low to high
threshold voltage
threshold voltage
0.5 * (V
TT
+ V
HYS_MIN
)
0.5 * (V
TT
+ V
HYS_MAX
)
V
4
4.
The V
TT
referred to in these specifications refers to instantaneous V
TT
.
V
T
-
Input high to low
threshold voltage
threshold voltage
0.5 * (V
TT
–
V
HYS_MAX
)
0.5 * (V
TT
– V
HYS_MIN
)
V
V
OH
Output High Voltage
N/A
V
TT
V
I
OL
Output Low Current
-
45
mA
5
5.
The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test
load.
load.
I
LI
Input Leakage Current
-
± 200
µA
6
6.
Leakage to V
SS
with land held at V
TT
.
I
LO
Output Leakage
Current
Current
-
± 200
µA
R
ON
Buffer On Resistance
7
12
Ω
Table 2-13. GTL+ Asynchronous Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1
NOTES:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage
0.0
V
TT
/2 – (0.10 * V
TT
)
-
2, 3
2.
V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3.
LINT0/INTR, LINT1/NMI, and FORCEPR# use GTLREF as a reference voltage. For these two signals,
V
V
IH
= GTLREF + (0.10 * V
TT
) and V
IL
= GTLREF – (0.10 * V
TT
).
V
IH
Input High Voltage
V
TT
/2 + (0.10 * V
TT
)
V
TT
-
, 4, 5, 6
4.
V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.
V
IH
and V
OH
may experience excursions above V
TT
.
6.
The V
TT
referred to in these specifications refers to instantaneous V
TT
.
V
OH
Output High Voltage
0.90*V
TT
V
TT
V
,
7
7.
All outputs are open drain.
I
OL
Output Low Current
—
V
TT
/[(0.50*R
TT_MIN
) +
R
ON_MIN
]
A
8
8.
The maximum output current is based on maximum current handling capability of the buffer and is not specified into the test
load.
load.
I
LI
Input Leakage Current
N/A
± 200
µA
9
9.
Leakage to V
SS
with land held at V
TT
.
I
LO
Output Leakage
Current
Current
N/A
± 200
µA
10
10.
Leakage to V
TT
with land held at 300 mV.
R
ON
Buffer On Resistance
8
12
Ω