Microchip Technology Microstick for the 5V PIC24F K-series DM240013-2 DM240013-2 Hoja De Datos

 2013 Microchip Technology Inc.

DS30003030B-page 223

The analog input model of the 12-bit A/D Converter is
shown in 

. The total sampling time for the

A/D is a function of the holding capacitor charge time.
For the A/D Converter to meet its specified accuracy, the
Charge Holding Capacitor (C

HOLD

) must be allowed to

fully charge to the voltage level on the analog input pin.
The Source Impedance (R

S

), the Interconnect Imped-

ance (R

IC

) and the Internal Sampling Switch Impedance

(R

SS

) combine to directly affect the time required to

charge C

HOLD

. The combined impedance of the analog

sources must, therefore, be small enough to fully charge
the holding capacitor within the chosen sample time. To
minimize the effects of pin leakage currents on the accu-
racy of the A/D Converter, the maximum recommended
source impedance, R

S

, is 2.5 k

. After the analog input

channel is selected (changed), this sampling function

must be completed prior to starting the conversion. The
internal holding capacitor will be in a discharged state
prior to each sample operation.
At least 1 T

AD

 time period should be allowed between

conversions for the sample time. For more details, see

Based on T

CY

 = 2/F

OSC

; Doze mode

and PLL are disabled.

 (ADCS + 1)

– 1

C

PIN

Rs

ANx

I

LEAKAGE

R

IC

 

 250

Sampling

Switch

R

SS

C

HOLD

V

SS

= 32 pF

500 nA

C

PIN

V

T

I

LEAKAGE

R

IC

R

SS

C

HOLD

= Input Capacitance
= Threshold Voltage
= Leakage Current at the Pin Due to

= Interconnect Resistance
= Sampling Switch Resistance
= Sample-and-Hold Capacitance (from DAC)

Various Junctions

 The C

PIN

 value depends on the device package and is not tested. The effect of C

PIN

 is negligible if Rs 

 5 k.

VA

R

SS

 

 3 k