Microchip Technology MA330028 Hoja De Datos
2011-2014 Microchip Technology Inc.
DS80000533H-page 11
dsPIC33EPXXXGP50X, dsPIC33EPXXXMC20X/50X and PIC24EPXXXGP/MC20X
13. Module: QEI
In Quadrature Encoder mode (CCM<1:0>
(QEIxCON<1:0>) = 00), the Index Counter
registers (INDXxCNTH and INDXxCNTL) cannot
be relied upon to increment when the last known
direction was positive and an index pulse occurs.
The Index Counter register can decrement even if
the last known direction was positive. This does
not apply to the External Clock or Internal Timer
QEI modes.
(QEIxCON<1:0>) = 00), the Index Counter
registers (INDXxCNTH and INDXxCNTL) cannot
be relied upon to increment when the last known
direction was positive and an index pulse occurs.
The Index Counter register can decrement even if
the last known direction was positive. This does
not apply to the External Clock or Internal Timer
QEI modes.
Work around
The index event can be used to implement a
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.
software counter. The direction could be
determined by comparing the current POSxCNT
value to that of the previous Index Event.
Affected Families and Silicon Revisions
14. Module: QEI
When Modulo Count mode (Mode 6) is selected
for the position counter (PIMOD<2:0>
(QEIxCON<12:10>) = 110), and the counter
direction is set to negative (CNTPOL
(QEIxCON<3>) = 1), the functions of the QEIxLEC
and QEIxGEC registers are reversed.
for the position counter (PIMOD<2:0>
(QEIxCON<12:10>) = 110), and the counter
direction is set to negative (CNTPOL
(QEIxCON<3>) = 1), the functions of the QEIxLEC
and QEIxGEC registers are reversed.
Work around
When using Modulo Count mode in conjunction
with a negative count direction (polarity), use the
QEIxLEC register as the upper count limit and the
QEIxGEC as the lower count limit.
with a negative count direction (polarity), use the
QEIxLEC register as the upper count limit and the
QEIxGEC as the lower count limit.
Affected Families and Silicon Revisions
15. Module: PWM
The PWM module can operate with variable
period, duty cycle, dead-time and phase values.
The master period and other timing parameters
can be updated in the same PWM cycle. With
immediate updates disabled, the new values
should take effect at the start of the next PWM
cycle.
period, duty cycle, dead-time and phase values.
The master period and other timing parameters
can be updated in the same PWM cycle. With
immediate updates disabled, the new values
should take effect at the start of the next PWM
cycle.
As a result of this issue, the updated master period
takes effect on the next PWM cycle, while the
update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:
takes effect on the next PWM cycle, while the
update of the additional timing parameter is
delayed by one PWM cycle. The parameters
affected by this erratum are as follows:
Master Period Registers – Update effective on the
next PWM cycle (PTPER).
next PWM cycle (PTPER).
Additional PWM Timing Parameters – Update
effective one PWM cycle after master period
update:
effective one PWM cycle after master period
update:
• Duty Cycle – PDCx and MDC registers
• Phase – PHASEx register
• Dead Time – DTRx and ALTDTRx registers
and dead-time compensation signals
• Clearing of current-limit and Fault conditions,
and application of External Period Reset signal
Work around
If the application requires the master period and
other parameters to be updated at the same time,
enable both immediate updates:
other parameters to be updated at the same time,
enable both immediate updates:
• EIPU (PTCON<10>) = 1 – To enable
immediate period updates
• IUE (PWMCONx<0>) = 1 – To enable
immediate updates of additional parameters
listed above
listed above
Enabling immediate updates will allow updates to
the master period and the other parameter to take
effect immediately after writing to the respective
registers.
the master period and the other parameter to take
effect immediately after writing to the respective
registers.
Affected Families and Silicon Revisions
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7
dsPIC33/PIC24EP32 devices
A3
dsPIC33/PIC24EP64 devices
A2, A3, A8
dsPIC33/PIC24EP128 devices
A3, A8
dsPIC33/PIC24EP256 devices
A3
dsPIC33/PIC24EP512 devices
A7