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Chapter 6 Parallel Input/Output Control
MC9S08DZ60 Series Data Sheet, Rev. 4
94
Freescale Semiconductor
6.5.2
Port B Registers
Port B is controlled by the registers listed below.
6.5.2.1
Port B Data Register (PTBD)
6.5.2.2
Port B Data Direction Register (PTBDD)
7
6
5
4
3
2
1
0
R
PTBD7
PTBD6
PTBD5
PTBD4
PTBD3
PTBD2
PTBD1
PTBD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-11. Port B Data Register (PTBD)
Table 6-9. PTBD Register Field Descriptions
Field
Description
7:0
PTBD[7:0]
Port B Data Register Bits — For port B pins that are inputs, reads return the logic level on the pin. For port B
pins that are configured as outputs, reads return the last value written to this register.
Writes are latched into all bits of this register. For port B pins that are configured as outputs, the logic level is
driven out the corresponding MCU pin.
Reset forces PTBD to all 0s, but these 0s are not driven out the corresponding pins because reset also configures
all port pins as high-impedance inputs with pull-ups/pull-downs disabled.
7
6
5
4
3
2
1
0
R
PTBDD7
PTBDD6
PTBDD5
PTBDD4
PTBDD3
PTBDD2
PTBDD1
PTBDD0
W
Reset:
0
0
0
0
0
0
0
0
Figure 6-12. Port B Data Direction Register (PTBDD)
Table 6-10. PTBDD Register Field Descriptions
Field
Description
7:0
PTBDD[7:0]
Data Direction for Port B Bits — These read/write bits control the direction of port B pins and what is read for
PTBD reads.
0 Input (output driver disabled) and reads return the pin value.
1 Output driver enabled for port B bit n and PTBD reads return the contents of PTBDn.