Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
88
Freescale Semiconductor
2.3.6
Port B Data Direction Register (DDRB)
Table 2-6. DDRA Register Field Descriptions
Field
Description
7-4,2
DDRA
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disable
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disable
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
3
DDRA
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if API_EXTCLK is enabled, it will be forced as output
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if API_EXTCLK is enabled, it will be forced as output
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
1
DDRA
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if XIRQ is enabled, it will be forced as input
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if XIRQ is enabled, it will be forced as input
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
0
DDRA
Port A Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if /IRQ is enabled, it will be forced as input
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
Else if /IRQ is enabled, it will be forced as input
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
Address 0x0003 (PRR)
Access: User read/write
1
1
Read: Anytime
Write: Anytime
Write: Anytime
7
6
5
4
3
2
1
0
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
Reset
0
0
0
0
0
0
0
0
Figure 2-4. Port B Data Direction Register (DDRB)