Freescale Semiconductor Demonstration Board for Freescale MC9S12XHY256 Microcontroller DEMO9S12XHY256 DEMO9S12XHY256 Manual De Usuario
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DEMO9S12XHY256
Port Integration Module (S12XHYPIMV1)
MC9S12XHY-Family Reference Manual, Rev. 1.04
Freescale Semiconductor
89
NOTE
Due to internal synchronization circuits, it can take up to 2 bus clock cycles
until the correct value is read on PTA, PTB registers, when changing the
DDRA,DDRB register.
until the correct value is read on PTA, PTB registers, when changing the
DDRA,DDRB register.
2.3.7
PIM Reserved Register
2.3.8
Ports A, B, BKGD pin Pull Control Register (PUCR)
Table 2-7. DDRB Register Field Descriptions
Field
Description
7-0
DDRB
Port B Data Direction—
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
This bit determines whether the associated pin is an input or output.
If corresponding LCD segment is enabled, it will be forced as input/output disabled
1 Associated pin is configured as output
0 Associated pin is configured as input
0 Associated pin is configured as input
Address 0x0004 (PRR) to 0x0009 (PRR)
Access: User read
1
1
Read: Always reads 0x00
Write: Unimplemented
Write: Unimplemented
7
6
5
4
3
2
1
0
R
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 2-5. PIM Reserved Register
Address 0x000C (PRR)
Access: User read/write
1
1
Read:Anytime in single-chip modes.
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
Write:Anytime, except BKPUE which is writable in Special Single-Chip Mode only.
7
6
5
4
3
2
1
0
R
0
BKPUE
0
0
0
0
PUPBE
PUPAE
W
Reset
0
1
0
0
0
0
1
1
= Unimplemented or Reserved
Figure 2-6. Ports AB, BKGD pin Pull Control Register (PUCR)