Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario

104

  Datasheet

The SMBus thermal sensor and its associated thermal diode are not related to, and are completely
independent of, the precision on-die temperature sensor and thermal control circuit (TCC) of the
Thermal Monitor feature discussed in 

.

The processor SMBus implementation uses the clock and data signals of the V1.1 System
Management Bus Specification. It does not implement the SMBSUS# signal. Layout and routing
guidelines are available in the appropriate platform design guidelines document.

For platforms which do not implement any of the SMBus features found on the processor, all of the
SMBus connections to the socket pins, 

, may be left unconnected (SM_ALERT#,

SM_CLK, SM_DAT, SM_EP_A[2:0], SM_TS_A[1:0], SM_WP). 

SM_V

CC

 provides power to the

VID generation logic in addition to supplying the SMBus and must be supplied with 3.3 volt power
to assure correct setting of the processor core voltage (V

CC

).

Actual implementation may vary. For use in general understanding of the architecture. All SMBus pull-up
and pull-down resistors are 10K ohms and located on the processor.

The lower half (128 bytes) of the SMBus memory component is an electrically programmed read-
only memory with information about the processor. This information is permanently write-
protected. 

 shows the data fields and formats provided in the Processor Information ROM

(PIROM).

SM_EP_A1

Processor

Information

ROM

and

Scratch

EEPROM

(1 Kbit each)

Thermal

Sensor

A0

A1

A2

WP

A0

A1

SM_EP_A0

SM_EP_A2

SM_TS_A0

SM_TS_A1

SM_VCC

CLK

CLK

DATA

DATA

VCC

VCC

VSS

VSS

STDBY#

ALERT#

SM_CLK

SM_DAT

SM_ALERT#

SM_WP