Manual De Usuario (UPG3843W)Tabla de contenidosIntroduction11Terminology12State of Data13References14Electrical Specifications15Front Side Bus and GTLREF15Power and Ground Pins15Decoupling Guidelines15Front Side Bus Clock (BCLK[1:0]) and Processor Clocking16PLL Filter17Front Side Bus-to-Core Frequency Ratio17Front Side Bus Clock Frequency Select Truth Table for BSEL[1:0]17Typical VCCIOPLL, VCCA and VSSA Power Distribution18Phase Lock Loop (PLL) Filter Requirements19Voltage Identification20Voltage Identification Definition21Reserved Or Unused Pins22Front Side Bus Signal Groups22Front Side Bus Signal Groups23Asynchronous GTL+ Signals24Maximum Ratings24Processor Absolute Maximum Ratings24Processor DC Specifications25Voltage and Current Specifications26Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID =1.5V)27Intel® Xeon™ Processor with 512 KB L2 Cache Voltage-Current (VID = 1.525V)28Front Side Bus Differential BCLK Specifications28AGTL+ Signal Group DC Specifications29TAP and PWRGOOD Signal Group DC Specifications29SMBus Signal Group DC Specifications30AGTL+ Front Side Bus Specifications31AGTL+ Bus Voltage Definitions31Front Side Bus AC Specifications32Front Side Bus Common Clock AC Specifications33Miscellaneous Signals+ AC Specifications34TAP Signal Group AC Specifications35Processor AC Timing Waveforms36Electrical Test Circuit37TCK Clock Waveform37Differential Clock Waveform38Differential Clock Crosspoint Specification38Front Side Bus Common Clock Valid Delay Timing Waveform39Front Side Bus Source Synchronous 2X (Address) Timing Waveform39Front Side Bus Source Synchronous 4X (Data) Timing Waveform40Front Side Bus Reset and Configuration Timing Waveform41Power-On Reset and Configuration Timing Waveform41TAP Valid Delay Timing Waveform42Test Reset (TRST#), Async GTL+ Input, and PROCHOT# Timing Waveform42THERMTRIP# to VCC Timing42SMBus Timing Waveform43SMBus Valid Delay Timing Waveform43Example 3.3 VDC/SM_VCC Sequencing44Front Side Bus Signal Quality Specifications45BCLK Signal Quality Specifications45Front Side Bus Signal Quality Specifications and Measurement Guidelines46BCLK[1:0] Signal Integrity Waveform46Buffers47Ringback Specifications for TAP Buffers47Buffers48Low-to-High Front Side Bus Receiver Ringback Tolerance for PWRGOOD TAP Buffers48Front Side Bus Signal Quality Specifications and Measurement Guidelines50Source Synchronous (200 MHz) AGTL+ Signal Group Overshoot/Undershoot Tolerance53Maximum Acceptable Overshoot/Undershoot Waveform55Mechanical Specifications57INT-mPGA Processor Package Assembly Drawing (Includes Socket)57Mechanical Specifications58INT-mPGA Processor Package Top View: Component Placement Detail58INT-mPGA Processor Package Drawing59INT-mPGA Processor Package Dimensions59INT-mPGA Processor Package Top View: Component Height Keep-in60INT-mPGA Processor Package Cross Section View: Pin Side Component Keep-in60INT-mPGA Processor Package: Pin Detail61Processor Package Load Specifications62IHS Flatness and Tilt Drawing62Insertion Specifications63Mass Specifications63Materials63Processor Mass63Markings64Processor Top-Side Markings64Processor Bottom-Side Markings64Pin-Out Diagram65Processor Pin Out Diagram: Top View65Processor Pin Out Diagram: Bottom View66Pin Listing and Signal Definitions67Processor Pin Assignments67Pin Listing by Pin Name67Signal Definitions84Signal Definitions84Thermal Specifications95Processor with Thermal and Mechanical Components - Exploded View95Thermal Specifications96Processor Thermal Design Power vs Electrical Projections for VID = 1.500V96Processor Thermal Design Power vs Electrical Projections for VID = 1.525V97Measurements for Thermal Specifications98Thermal Measurement Point for Processor TCASE98Features99Power-On Configuration Options99Clock Control and Low Power States99Power-On Configuration Option Pins99Stop Clock State Machine100Thermal Monitor102System Management Bus (SMBus) Interface103Logical Schematic of SMBus Circuitry104Read Byte SMBus Packet107Write Byte SMBus Packet108Send Byte SMBus PacketReceive Byte SMBus Packet109SMBus Thermal Sensor Command Byte Bit Assignments109SMBus Thermal Sensor Status Register111SMBus Thermal Sensor Conversion Rate Registers112Thermal Sensor SMBus Addressing114Boxed Processor Specifications115Introduction115Mechanical Specifications116sors116Retention Mechanism118Boxed Processor Clip119Multiple View Space Requirements for the Boxed Processor120Fan Connector Electrical Pin Sequence121Fan Cable Connector Requirements122Processor Wind Tunnel General Dimensions123Processor Wind Tunnel Detailed Dimensions1241U Rack Mount Server Solution125Exploded View of the 1U Thermal Solution125Assembled View of the 1U Thermal Solution126Thermal Specifications127Debug Tools Specifications128Logic Analyzer Interface (LAI)128Tamaño: 2 MBPáginas: 129Language: EnglishManuales abiertas
