Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario
Los códigos de productos
UPG3843W
Intel® Xeon™ Processor with 512 KB L2 Cache
30
Datasheet
3. TAP signal group must meet the system signal quality specification in Chapter 3.0.
4. Refer to the Intel
4. Refer to the Intel
®
Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
5. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
6. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
7. V
OL_MAX
of 0.300V is guaranteed when driving a test load.
8. V
HYS
represents the amount of hysteresis, nominally centered about 0.5*V
CC
, for all TAP inputs.
9. Leakage to V
CC
with Pin held at 300 mV.
10.Leakage to V
SS
with pin held at V
CC
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. All outputs are open drain
3. V
2. All outputs are open drain
3. V
IH
is defined as the minimum voltage level at a receiving agent that will be interpreted as a logical high
value.
4. V
IL
is defined as the maximum voltage level at a receiving agent that will be interpreted as a logical low value.
5. V
IH
and V
OH
may experience excursions above V
CC
. However, input signal drivers must comply with the
6. Refer to the Intel
®
Xeon™ Processor with 512 KB L2 Cache Signal Integrity Models for I/V characteristics.
7. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
8. The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9. V
OL_MAX
, with R
TT
enabled.
10. Leakage to V
CC
with Pin held at 300 mV.
11. Leakage to V
SS
with pin held at V
CC
.
Table 11. SMBus Signal Group DC Specifications
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
2. These parameters are based on design characterization and are not tested.
3. All DC specifications for the SMBus signal group are measured at the processor pins.
4. Platform designers may need this value to calculate the maximum loading of the SMBus and to determine
maximum rise and fall times for SMBus signals.
Table 10. Asynchronous GTL+ Signal Group DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes
1, 7
V
IH
Input High Voltage
1.10 * GTLREF
V
CC
V
3, 5, 7
V
IL
Input Low Voltage
0.0
0.90 * GTLREF
V
4, 6
V
OH
Output High Voltage
N/A
V
CC
V
2, 5, 7
I
OL
Output Low Current
50
mA
8, 9
I
HI
Pin Leakage High
N/A
100
µA
11
I
LO
Pin Leakage Low
N/A
500
µA
10
R
ON
Buffer On Resistance
7
11
Ω
6
Symbol
Parameter
Min
Max
Unit
Notes
1, 2, 3
V
IL
Input Low Voltage
-0.30
0.30 * SM_V
CC
V
V
IH
Input High Voltage
0.70 * SM_V
CC
3.465
V
V
OL
Output Low Voltage
0
0.400
V
I
OL
Output Low Current
N/A
3.0
mA
I
LI
Input Leakage Current
N/A
±
10
µA
I
LO
Output Leakage Current
N/A
±
10
µA
C
SMB
SMBus Pin Capacitance
15.0
pF
4