Toshiba Xeon 2.8GHz UPG3843W Manual De Usuario

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2. The processor core clock frequency is derived from BCLK.
3. The period specified here is the average period. A given period may vary from this specification as governed

by the period stability specification (T2).

4. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
5. In this context, period stability is defined as the worst case timing difference between successive crossover

voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.

6. Slew rate is measured between the 35% and 65% points of the clock swing (V

L

 and V

H

).

.

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies and cache sizes.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V

CROSS

) of the

BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.

4. Valid delay timings for these signals are specified into the test circuit described in 

 and with GTLREF

at 2/3 * V

CC

 

± 2%.

5. Specification is for a minimum swing defined between AGTL+ V

IL_MAX

 to V

IH_MIN

. This assumes an edge rate

of

 

0.3 V/nS to 4.0 V/nS.

6. RESET# can be asserted (active) asynchronously, but must be deasserted synchronously.
7. This should be measured after V

CC

 and BCLK[1:0] become stable.

8. Maximum specification applies only while PWRGOOD is asserted.

.

T10: Common Clock Output Valid Delay

0.12

1.27

nS

4

T11: Common Clock Input Setup Time

0.65

N/A

nS

5

T12: Common Clock Input Hold Time

0.40

N/A

nS

5

T13: RESET# Pulse Width

1.00

10.00

mS

6, 7, 8

T20: Source Sync. Output Valid Delay (first data/
address only)

0.20

1.30

nS

1, 2, 3, 4, 

5

T21: T

VBD

 Source Sync. Data Output Valid Before 

Data Strobe

0.85

nS

1, 2, 3, 4, 

5, 8

T22: T

VAD

 Source Sync. Data Output Valid After 

Data Strobe

0.85

nS

1, 2, 3, 4, 

5, 8

T23: T

VBA

 Source Sync. Address Output Valid 

Before Address Strobe

1.88

nS

1, 2, 3, 4, 

5, 8

T24: T

VAA

 Source Sync. Address Output Valid After 

Address Strobe

1.88

nS

1, 2, 3, 4, 

5, 9

T25: T

SUSS

 Source Sync. Input Setup Time

0.21

nS

1, 2, 3, 4, 

6

T26: T

HSS

 Source Sync. Input Hold Time

0.21

nS

1, 2, 3, 4, 

6

T27: T

SUCC

 Source Sync. Input Setup Time to 

BCLK

0.65

nS

1, 2, 3, 4, 

7

T28: T

FASS

 First Address Strobe to Second Address 

Strobe

1/2

BCLKs

1, 2, 3, 4, 

10, 14