Analog Devices ADP5024 Evaluation Board ADP5024CP-EVALZ ADP5024CP-EVALZ Hoja De Datos
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ADP5024CP-EVALZ
Data Sheet
ADP5024
Rev. E | Page 25 of 28
Switching losses are associated with the current drawn by the
driver to turn on and turn off the power devices at the switching
frequency. The amount of switching power loss is given by
P
SW
= (C
GATE-P
+ C
GATE-N
) × V
IN1
2
× f
SW
(10)
where:
C
GATE-P
is the P-MOSFET gate capacitance.
C
GATE-N
is the N-MOSFET gate capacitance.
For the
, the total of (C
GATE-P
+ C
GATE-N
) is approx-
imately 150 pF.
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
The transition losses occur because the P-channel power
MOSFET cannot be turned on or off instantaneously, and the
SW node takes some time to slew from near ground to near
V
OUT1
(and from V
OUT1
to ground). The amount of transition
loss is calculated by
P
TRAN
= V
IN1
× I
OUT1
× (t
RISE
+ t
FALL
) × f
SW
(11)
where t
RISE
and t
FALL
are the rise time and the fall time of the
switching node, SW. For the
, the rise and fall times of
SW are in the order of 5 ns.
If the preceding equations and parameters are used for estimating
the converter efficiency, it must be noted that the equations do
If the preceding equations and parameters are used for estimating
the converter efficiency, it must be noted that the equations do
not describe all of the converter losses, and the parameter values
given are typical numbers. The converter performance also
depends on the choice of passive components and board layout;
therefore, include a sufficient safety margin in the estimate.
LDO Regulator Power Dissipation
The power loss of the LDO regulator is given by
P
DLDO
= [(V
IN
− V
OUT
) × I
LOAD
] + (V
IN
× I
GND
)
(12)
where:
I
LOAD
is the load current of the LDO regulator.
V
IN
and V
OUT
are input and output voltages of the LDO,
respectively.
I
GND
is the ground current of the LDO regulator.
Power dissipation due to the ground current is small, and it
can be ignored.
JUNCTION TEMPERATURE
In cases where the board temperature, T
A
, is known, the
thermal resistance parameter, θ
JA
, can be used to estimate the
junction temperature rise. T
J
is calculated from T
A
and P
D
using
the formula
T
J
= T
A
+ (P
D
× θ
JA
)
(14)
The typical θ
JA
value for the 24-lead, 4 mm × 4 mm LFCSP is
35°C/W (see Table 7). A very important factor to consider is
that θ
JA
is based on a 4-layer, 4 in × 3 in, 2.5 oz copper, as per
JEDEC standard, and real applications may use different sizes
and layers. To remove heat from the device, it is important to
and layers. To remove heat from the device, it is important to
maximize the use of copper. Copper exposed to air dissipates
heat better than copper used in the inner layers. Connect the
exposed pad to the ground plane with several vias.
If the case temperature can be measured, the junction temperature
If the case temperature can be measured, the junction temperature
is calculated by
T
J
= T
C
+ (P
D
× θ
JC
)
(15)
where T
C
is the case temperature and θ
JC
is the junction-to-case
thermal resistance provided in Table 7.
When designing an application for a particular ambient
temperature range, calculate the expected
When designing an application for a particular ambient
temperature range, calculate the expected
dissipation (P
D
) due to the losses of all channels by using
Equation 8 to Equation 13. From this power calculation, the
junction temperature, T
J
, can be estimated using Equation 14.
The reliable operation of the converter and the LDO regulator
can be achieved only if the estimated die junction temperature of
the
the
and mean time between failures (MTBF) is highly affected by
increasing the junction temperature. Additional information
about product reliability can be found from the ADI Reliability
Handbook, which is available at the following URL:
The total power dissipation in the
P
D
= P
DBUCK1
+ P
DBUCK2
+ P
DLDO
(13)