Analog Devices ADP1879 Evaluation Board ADP1879-1.0-EVALZ ADP1879-1.0-EVALZ Hoja De Datos
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ADP1879-1.0-EVALZ
Data
Sheet
ADP1878/ADP1879
Rev. B | Page 17 of 40
THEORY OF OPERATION
BLOCK DIAGRAM
Figure 64.
Block Diagram
The
are versatile current-mode, synchronous
step-down controllers that provide superior transient response,
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current
sense gain, current control scheme. In addition, these devices offer
optimal stability, and current-limit protection by using a constant
on time, pseudo fixed frequency with a programmable current
sense gain, current control scheme. In addition, these devices offer
optimum performance at low duty cycles by using a valley, current-
mode control architecture. This allows the
mode control architecture. This allows the
to drive all N-channel power stages to regulate output voltages
to as low as 0.6 V.
to as low as 0.6 V.
09441-
064
DRVH
GND
IREV
COMP
COMP
ADP1878/ADP1879
C
R (TRIMMED)
VREG
t
ON
TIMER
t
ON
= 2RC(V
OUT
/V
IN
)
I
SW
INFORMATION
SW FILTER
STATE
MACHINE
TON
BG_REF
IN_PSM
IN_SS
PWM
COMP
HS_0
HS
SW
LS
LS_0
IREV
LEVEL
SHIFT
HS
VREG
LS
VREG
300kΩ
800kΩ
8kΩ
SW
DRVL
PGND
BST
VIN
PSM
REF_ZERO
IN_HICCUP
SS
COMP
COMP
ERROR
AMP
AMP
SS_REF
0.6V
LOWER
COMP
CLAMP
REF_ZERO
CS
AMP
PWM
FB
COMP
VREG
I
SS
SS
0.4V
ADC
RES DETECT AND
GAIN SET
GAIN SET
CS GAIN SET
BIAS BLOCK
AND REFERENCE
REF
LDO
PRECISION
ENABLE
ENABLE
630mV
TO ENABLE
ALL BLOCKS
ALL BLOCKS
EN
RES
530mV
690mV
FB
600mV
PGOOD
THRESHOLD/
HYSTERESIS