Analog Devices ADP1879 Evaluation Board ADP1879-1.0-EVALZ ADP1879-1.0-EVALZ Hoja De Datos

 

Rev. B | Page 26 of 40 

An important criteria to consider in constructing a dc-to-dc 
converter is efficiency. By definition, efficiency is the ratio of the 
output power to the input power. For high power applications at 
load currents of up to 20 A, the following are important MOSFET 
parameters that aid in the selection process: 

  V

GS (TH)

 is the MOSFET voltage applied between the gate 

and the source that starts channel conduction. 

  R

DS (ON)

 is the on resistance of the MOSFET during channel 

conduction. 

  Q

G

 is the total gate charge. 

  C

N1

 is the input capacitance of the high-side switch. 

  C

N2

 is the input capacitance of the low-side switch. 

The following are the losses experienced through the external 
component during normal switching operation: 

  Channel conduction loss (both of the MOSFETs). 
  MOSFET driver loss. 
  MOSFET switching loss. 
  Body diode conduction loss (low-side MOSFET). 
  Inductor loss (copper and core loss). 

During normal operation, the bulk of the loss in efficiency is due 
to the power dissipated through MOSFET channel conduction. 
Power loss through the high-side MOSFET is directly proportional 
to the duty cycle (D) for each switching period, and the power 
loss through the low-side MOSFET is directly proportional to  
1 − D for each switching period. The selection of MOSFETs is 
governed by the maximum dc load current that the converter is 
expected to deliver. In particular, the selection of the low-side 
MOSFET is dictated by the maximum load current because a 
typical high current application employs duty cycles of less than 
50%. Therefore, the low-side MOSFET is in the on state for 
most of the switching period.  

1, 2

1

 

Other dissipative elements are the MOSFET drivers. The con-
tributing factors are the dc current flowing through the driver 
during operation and the Q

GATE

 parameter of the external MOSFETs. 

 = [V

 × (f

 + I

)] + [V

 × 

(f

)] 

where: 
C

 is the input gate capacitance of the high-side MOSFET. 

 is the input gate capacitance of the low-side MOSFET. 

 is the dc current flowing into the high- and low-side drivers. 

 is the driver bias voltage (that is, the low input voltage (V

) 

minus the rectifier drop (see Figure 83)). 
V

 is the bias voltage. 

The SW node transitions due to the switching activities of the 
high- and low-side MOSFETs. This causes removal and reple-
nishing of charge to and from the gate oxide layer of the MOSFET, 
as well as to and from the parasitic capacitance associated with 
the gate oxide edge overlap and the drain and source terminals. 
The current that enters and exits these charge paths presents 
additional loss during these transition times. This can be approxi-
mately quantified by using the following equation, which represents 
the time in which charge enters and exits these capacitive regions: 

 = R

 × C

  

where: 
C

 is the C

GD

 + C

GS

 of the external MOSFET.  

 is the gate input resistance of the external MOSFET. 

The ratio of this time constant to the period of one switching cycle 
is the multiplying factor to be used in the following expression: 

-TRANS

2 

or 

 = f

 × R

 × C

 × I

 × V

 × 2 

The 

 employ anti cross conduction circuitry 

that prevents the high- and low-side MOSFETs from conducting 
current simultaneously. This overlap control is beneficial, avoiding 
large current flow that may lead to irreparable damage to the 
external components of the power stage. However, this blanking 
period comes with the trade-off of a diode conduction loss 
occurring immediately after the MOSFETs change states and 
continuing well into idle mode.  

 

 

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