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ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1200
The back off time is based on an XOR of the 10 least significant bits of the data coming from FIFO and a 10-bit
pseudo random number generator. The number of bits used depends on the number of collisions seen. After the
first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used
above ten collisions. An error will be indicated and no further attempts will be made if 16 consecutive attempts
cause collision. This operation is compliant with the description in Clause 4.2.3.2.5 of the IEEE 802.3 standard
which refers to the truncated binary exponential back off algorithm.
pseudo random number generator. The number of bits used depends on the number of collisions seen. After the
first collision 1 bit is used, then the second 2 bits and so on up to the maximum of 10 bits. All 10 bits are used
above ten collisions. An error will be indicated and no further attempts will be made if 16 consecutive attempts
cause collision. This operation is compliant with the description in Clause 4.2.3.2.5 of the IEEE 802.3 standard
which refers to the truncated binary exponential back off algorithm.
In 10/100 mode, both collisions and late collisions are treated identically, and back off and retry will be performed
up to 16 times. This condition is reported in the transmit buffer descriptor word 1 (late collision, bit 26) and also in
the Transmit Status Register (late collision, bit 7). An interrupt can also be generated (if enabled) when this
exception occurs, and bit 5 in the Interrupt Status Register will be set.
up to 16 times. This condition is reported in the transmit buffer descriptor word 1 (late collision, bit 26) and also in
the Transmit Status Register (late collision, bit 7). An interrupt can also be generated (if enabled) when this
exception occurs, and bit 5 in the Interrupt Status Register will be set.
In all modes of operation, if the transmit DMA underruns, a bad CRC is automatically appended using the same
mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system this should never
happen.
mechanism as jam insertion and the GTXER signal is asserted. For a properly configured system this should never
happen.
By setting when bit 28 is set in the Network Configuration Register, the Inter Packet Gap (IPG) may be stretched
beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG
Stretch Register (GMAC_IPGS). The least significant 8 bits of the IPG Stretch Register multiply the previous frame
length (including preamble). The next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length
to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration
Register. The IPG Stretch Register cannot be used to shrink the IPG below 96 bits.
beyond 96 bits depending on the length of the previously transmitted frame and the value written to the IPG
Stretch Register (GMAC_IPGS). The least significant 8 bits of the IPG Stretch Register multiply the previous frame
length (including preamble). The next significant 8 bits (+1 so as not to get a divide by zero) divide the frame length
to generate the IPG. IPG stretch only works in full duplex mode and when bit 28 is set in the Network Configuration
Register. The IPG Stretch Register cannot be used to shrink the IPG below 96 bits.
If the back pressure bit is set in the Network Control Register, or if the HDFC configuration bit is set in the
GMAC_UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a collision.
This provides a way of implementing flow control in half duplex mode.
GMAC_UR register (10M or 100M half duplex mode), the transmit block transmits 64 bits of data, which can
consist of 16 nibbles of 1011 or in bit rate mode 64 1s, whenever it sees an incoming frame to force a collision.
This provides a way of implementing flow control in half duplex mode.
43.5.5 MAC Receive Block
All processing within the MAC receive block is implemented using a 16-bit data path. The MAC receive block
checks for valid preamble, FCS, alignment and length, presents received frames to FIFO and stores the frame
destination address for use by the address checking block.
checks for valid preamble, FCS, alignment and length, presents received frames to FIFO and stores the frame
destination address for use by the address checking block.
If, during the frame reception, the frame is found to be too long, a bad frame indication is sent to FIFO. The
receiver logic ceases to send data to memory as soon as this condition occurs.
receiver logic ceases to send data to memory as soon as this condition occurs.
At end of frame reception the receive block indicates to the DMA block whether the frame is good or bad. The DMA
block will recover the current receive buffer if the frame was bad.
block will recover the current receive buffer if the frame was bad.
Ethernet frames are normally stored in DMA memory or to FIFO complete with the FCS. Setting the FCS remove
bit in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The reported
frame length field is reduced by four bytes to reflect this operation.
bit in the network configuration (bit 17) causes frames to be stored without their corresponding FCS. The reported
frame length field is reduced by four bytes to reflect this operation.
The receive block signals to the register block to increment the alignment, CRC (FCS), short frame, long frame,
jabber or receive symbol errors when any of these exception conditions occur.
jabber or receive symbol errors when any of these exception conditions occur.
If bit 26 is set in the network configuration, CRC errors will be ignored and CRC errored frames will not be
discarded, though the Frame Check Sequence Errors statistic register will still be incremented. Additionally, if
configured to use the DMA and not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1
will be updated to indicate the FCS validity for the particular frame. This is useful for applications such as
EtherCAT whereby individual frames with FCS errors must be identified.
discarded, though the Frame Check Sequence Errors statistic register will still be incremented. Additionally, if
configured to use the DMA and not enabled for jumbo frames mode, then bit[13] of the receiver descriptor word 1
will be updated to indicate the FCS validity for the particular frame. This is useful for applications such as
EtherCAT whereby individual frames with FCS errors must be identified.
Received frames can be checked for length field error by setting the length field error frame discard bit of the
Network Configuration Register (bit-16). When this bit is set, the receiver compares a frame's measured length
with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded if the measured length is
shorter. This checking procedure is for received frames between 64 bytes and 1518 bytes in length.
Network Configuration Register (bit-16). When this bit is set, the receiver compares a frame's measured length
with the length field (bytes 13 and 14) extracted from the frame. The frame is discarded if the measured length is
shorter. This checking procedure is for received frames between 64 bytes and 1518 bytes in length.