Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Hoja De Datos
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ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1202
the frame, is the group or individual bit. This is one for multicast addresses and zero for unicast. The all ones
address is the broadcast address and a special case of multicast.
address is the broadcast address and a special case of multicast.
The GMAC supports recognition of four specific addresses. Each specific address requires two registers, Specific
Address Register Bottom and Specific Address Register Top. Specific Address Register Bottom stores the first
four bytes of the destination address and Specific Address Register Top contains the last two bytes. The
addresses stored can be specific, group, local or universal.
Address Register Bottom and Specific Address Register Top. Specific Address Register Bottom stores the first
four bytes of the destination address and Specific Address Register Top contains the last two bytes. The
addresses stored can be specific, group, local or universal.
The destination address of received frames is compared against the data stored in the Specific Address Registers
once they have been activated. The addresses are deactivated at reset or when their corresponding Specific
Address Register Bottom is written. They are activated when Specific Address Register Top is written. If a receive
frame address matches an active address, the frame is written to FIFO and on to DMA memory if used.
once they have been activated. The addresses are deactivated at reset or when their corresponding Specific
Address Register Bottom is written. They are activated when Specific Address Register Top is written. If a receive
frame address matches an active address, the frame is written to FIFO and on to DMA memory if used.
Frames may be filtered using the type ID field for matching. Four type ID registers exist in the register address
space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When
a frame is received, the matching is implemented as an OR function of the various types of match.
space and each can be enabled for matching by writing a one to the MSB (bit 31) of the respective register. When
a frame is received, the matching is implemented as an OR function of the various types of match.
The contents of each type ID register (when enabled) are compared against the length/type ID of the frame being
received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a
match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the receive buffer descriptor status
are set indicating which type ID register generated the match, if the receive checksum offload is disabled.
received (e.g., bytes 13 and 14 in non-VLAN and non-SNAP encapsulated frames) and copied to memory if a
match is found. The encoded type ID match bits (Word 0, Bit 22 and Bit 23) in the receive buffer descriptor status
are set indicating which type ID register generated the match, if the receive checksum offload is disabled.
The reset state of the type ID registers is zero, hence each is initially disabled.
The following example illustrates the use of the address and type ID match registers for a MAC address of
21:43:65:87:A9:CB:
21:43:65:87:A9:CB:
Note:
1.
Contains the address of the transmitting device
The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom
as shown. For a successful match to specific address 1, the following address matching registers must be set up:
as shown. For a successful match to specific address 1, the following address matching registers must be set up:
Specific Address 1 Bottom [31:0] Register (GMAC_SAB1) (Address 0x088) 0x87654321
Specific Address 1 Top [47:32] Register (GMAC_SAT1) (Address 0x08C) 0x0000CBA9
Preamble
55
SFD
D5
DA (Octet 0 - LSB)
21
DA (Octet 1)
43
DA (Octet 2)
65
DA (Octet 3)
87
DA (Octet 4)
A9
DA (Octet 5 - MSB)
CB
SA (LSB)
00
SA
00
SA
00
SA
00
SA
00
SA (MSB)
00
Type ID (MSB)
43
Type ID (LSB)
21