Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos

181

SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]

11063K–ATARM–05-Nov-13

Code Example: 

write_register(CKGR_PLLBR,0x00040805)

If PLL B and divider B are enabled, the PLL B input clock is the main clock. PLL B output clock is PLL B input clock 
multiplied by 5. Once CKGR_PLLBR has been written, LOCKB bit will be set after eight slow clock cycles.

4.

Selection of Master Clock and Processor Clock

The Master Clock and the Processor Clock are configurable via the PMC_MCKR register.

The CSS field is used to select the clock source of the Master Clock and Processor Clock dividers. By default, the 
selected clock source is main clock.

The PRES field is used to control the Master/Processor Clock prescaler. The user can choose between different 
values (1, 2, 4, 8, 16, 32, 64). Prescaler output is the selected clock source divided by PRES parameter. By 
default, PRES parameter is set to 1 which means that the input clock of the Master Clock and Processor Clock 
dividers is equal to slow clock.

The MDIV field is used to control the Master Clock divider. It is possible to choose between different values (0, 1, 
2, 3). The Master Clock output is Master/Processor Clock Prescaler output divided by 1, 2, 4 or 3, depending on 
the value programmed in MDIV.

The PLLADIV2 field is used to control the PLLA Clock divider. It is possible to choose between different values (0, 
1). The PMC PLLA Clock input is divided by 1 or 2, depending on the value programmed in PLLADIV2.

By default, MDIV and PLLADIV2 are set to 0, which indicates that Processor Clock is equal to the Master Clock.

Once the PMC_MCKR register has been written, the user must wait for the MCKRDY bit to be set in the PMC_SR 
register. This can be done either by polling the status register or by waiting for the interrupt line to be raised if the 
associated interrupt to MCKRDY has been enabled in the PMC_IER register.

The PMC_MCKR register must not be programmed in a single write operation. The preferred programming 
sequence for the PMC_MCKR register is as follows:



If a new value for CSS field corresponds to PLLA Clock,



Program the PRES field in the PMC_MCKR register.



Wait for the MCKRDY bit to be set in the PMC_SR register.



Program the CSS field in the PMC_MCKR register.



Wait for the MCKRDY bit to be set in the PMC_SR register.



If a new value for CSS field corresponds to Main Clock or Slow Clock,



Program the CSS field in the PMC_MCKR register.



Wait for the MCKRDY bit to be set in the PMC_SR register.



Program the PRES field in the PMC_MCKR register.



Wait for the MCKRDY bit to be set in the PMC_SR register.

If at some stage one of the following parameters, CSS or PRES, is modified, the MCKRDY bit will go low to indi-
cate that the Master Clock and the Processor Clock are not ready yet. The user must wait for MCKRDY bit to be 
set again before using the Master and Processor Clocks.

Note:

IF PLLA clock was selected as the Master Clock and the user decides to modify it by writing in CKGR_PLLAR, 
the MCKRDY flag will go low while PLLA is unlocked. Once PLLA is locked again, LOCK goes high and 
MCKRDY is set.
While PLLA is unlocked, the Master Clock selection is automatically changed to Main Clock. For further informa-
tion, see 

.

Code Example: 

write_register(PMC_MCKR,0x00000001)

wait (MCKRDY=1)

write_register(PMC_MCKR,0x00000011)

wait (MCKRDY=1)

The Master Clock is main clock divided by 16.

The Processor Clock is the Master Clock.