Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Hoja De Datos
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AT91SAM9N12-EK
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SAM9N12/SAM9CN11/SAM9CN12 [DATASHEET]
11063K–ATARM–05-Nov-13
5.
Selection of Programmable clocks
Programmable clocks are controlled via registers; PMC_SCER, PMC_SCDR and PMC_SCSR.
Programmable clocks can be enabled and/or disabled via the PMC_SCER and PMC_SCDR registers. Depending
on the system used, 2 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indica-
tion as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
on the system used, 2 programmable clocks can be enabled or disabled. The PMC_SCSR provides a clear indica-
tion as to which Programmable clock is enabled. By default all Programmable clocks are disabled.
PMC_PCKx registers are used to configure programmable clocks.
The CSS and CSSMCK fields are used to select the programmable clock divider source. Five clock options are
available: main clock, slow clock, master clock, PLLACK, UPLLCK. By default, the clock source selected is slow
clock.
available: main clock, slow clock, master clock, PLLACK, UPLLCK. By default, the clock source selected is slow
clock.
The PRES field is used to control the programmable clock prescaler. It is possible to choose between different val-
ues (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default,
the PRES parameter is set to 1 which means that master clock is equal to slow clock.
ues (1, 2, 4, 8, 16, 32, 64). Programmable clock output is prescaler input divided by PRES parameter. By default,
the PRES parameter is set to 1 which means that master clock is equal to slow clock.
Once the PMC_PCKx register has been programmed, The corresponding programmable clock must be enabled
and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either
by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has
been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
and the user is constrained to wait for the PCKRDYx bit to be set in the PMC_SR register. This can be done either
by polling the status register or by waiting the interrupt line to be raised if the associated interrupt to PCKRDYx has
been enabled in the PMC_IER register. All parameters in PMC_PCKx can be programmed in a single write
operation.
If the CSS and PRES parameters are to be modified, the corresponding programmable clock must be disabled
first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable
clock and wait for the PCKRDYx bit to be set.
first. The parameters can then be modified. Once this has been done, the user must re-enable the programmable
clock and wait for the PCKRDYx bit to be set.
Code Example:
write_register(PMC_PCK0,0x00000015)
Programmable clock 0 is main clock divided by 32.
6.
Enabling Peripheral Clocks
Once all of the previous steps have been completed, the peripheral clocks can be enabled and/or disabled via reg-
isters PMC_PCER and PMC_PCDR.
isters PMC_PCER and PMC_PCDR.
Depending on the system used, 19 peripheral clocks can be enabled or disabled. The PMC_PCR provides a clear
view as to which peripheral clock is enabled.
view as to which peripheral clock is enabled.
Note:
Each enabled peripheral clock corresponds to Master Clock.
Code Examples:
write_register(PMC_PCER,0x00000110)
Peripheral clocks 4 and 8 are enabled.
write_register(PMC_PCDR,0x00000010)
Peripheral clock 4 is disabled.