Atmel Evaluation Kit AT91SAM9M10-G45-EK AT91SAM9M10-G45-EK Hoja De Datos
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AT91SAM9M10-G45-EK
504
SAM9M10 [DATASHEET]
6355F–ATARM–12-Mar-13
31.7.7.5
Character Transmission
The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status
bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is
empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the
current character processing is completed, the last character written in US_THR is transferred into the Shift Regis-
ter of the transmitter and US_THR becomes empty, thus TXRDY rises.
bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is
empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the
current character processing is completed, the last character written in US_THR is transferred into the Shift Regis-
ter of the transmitter and US_THR becomes empty, thus TXRDY rises.
Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while
TXRDY is low has no effect and the written character is lost.
TXRDY is low has no effect and the written character is lost.
If the USART is in SPI Slave Mode and if a character must be sent while the Transmit Holding Register (US_THR)
is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time.
The UNRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
is empty, the UNRE (Underrun Error) bit is set. The TXD transmission line stays at high level during all this time.
The UNRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
In SPI Master Mode, the slave select line (NSS) is asserted at low level 1 Tbit before the transmission of the MSB
bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order
to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line
(NSS) can be forced at low level by writing the Control Register (US_CR) with the RTSEN bit at 1. The slave select
line (NSS) can be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit at 1 (for
example, when all data have been transferred to the slave device).
bit and released at high level 1 Tbit after the transmission of the LSB bit. So, the slave select line (NSS) is always
released between each character transmission and a minimum delay of 3 Tbits always inserted. However, in order
to address slave devices supporting the CSAAT mode (Chip Select Active After Transfer), the slave select line
(NSS) can be forced at low level by writing the Control Register (US_CR) with the RTSEN bit at 1. The slave select
line (NSS) can be released at high level only by writing the Control Register (US_CR) with the RTSDIS bit at 1 (for
example, when all data have been transferred to the slave device).
In SPI Slave Mode, the transmitter does not require a falling edge of the slave select line (NSS) to initiate a charac-
ter transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least
1 Tbit before the first serial clock cycle corresponding to the MSB bit.
ter transmission but only a low level. However, this low level must be present on the slave select line (NSS) at least
1 Tbit before the first serial clock cycle corresponding to the MSB bit.
31.7.7.6
Character Reception
When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the
RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while RXRDY is set, the OVRE
(Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The
OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1.
To ensure correct behavior of the receiver in SPI Slave Mode, the master device sending the frame must ensure a
minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present
on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
minimum delay of 1 Tbit between each character transmission. The receiver does not require a falling edge of the
slave select line (NSS) to initiate a character reception but only a low level. However, this low level must be present
on the slave select line (NSS) at least 1 Tbit before the first serial clock cycle corresponding to the MSB bit.
31.7.7.7
Receiver Timeout
Because the receiver baudrate clock is active only during data transfers in SPI Mode, a receiver timeout is impos-
sible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).
sible in this mode, whatever the Time-out value is (field TO) in the Time-out Register (US_RTOR).