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ATSAM4S-XPLD
1020
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
42.6
Functional Description
42.6.1 Digital-to-Analog Conversion
The DACC uses the master clock (MCK) divided by two to perform conversions.
This clock is named DACC Clock.
Once a conversion starts the DACC takes
25 clock periods to provide the analog result on the selected analog
output.
42.6.2 Conversion Results
When a conversion is completed, the resulting analog value is available at the selected DACC channel output and the
EOC bit in the
EOC bit in the
, is set.
Reading the DACC_ISR register clears the EOC bit.
42.6.3 Conversion Triggers
In free running mode, conversion starts as soon as at least one channel is enabled and data is written in the
, then
25
DACC Clock periods later, the converted data is available at the corresponding
analog output as stated above.
In external trigger mode, the conversion waits for a rising edge on the selected trigger to begin.
Warning: Disabling the external trigger mode automatically sets the DACC in free running mode.
42.6.4 Conversion FIFO
A 4 half-word FIFO is used to handle the data to be converted.
As long as the TXRDY flag in the
is active the DAC Controller is ready to accept
. Data which cannot be converted immediately
are stored in the DACC FIFO.
When the FIFO is full or the DACC is not ready to accept conversion requests, the TXRDY flag is inactive.
The WORD field of the
allows the user to switch between half-word and word transfer for writing
into the FIFO.
In half-word transfer mode only the 16 LSB of DACC_CDR data are taken into account, DACC_CDR[15:0] is stored into
the FIFO.
the FIFO.
DACC_CDR[11:0] field is used as data and the DACC_CDR[15:12] bits are used for channel selection if the TAG field is
set in DACC_MR register.
set in DACC_MR register.
In word transfer mode each time the DACC_CDR register is written 2 data items are stored in the FIFO. The first data
item sampled for conversion is DACC_CDR[15:0] and the second DACC_CDR[31:16].
item sampled for conversion is DACC_CDR[15:0] and the second DACC_CDR[31:16].
Fields DACC_CDR[15:12] and DACC_CDR[31:28] are used for channel selection if the TAG field is set in DACC_MR
register.
register.
Warning: Writing in the DACC_CDR register while TXRDY flag is inactive will corrupt FIFO data.
42.6.5 Channel Selection
There are two means by which to select the channel to perform data conversion.
. Data requests will merely be converted to the channel selected with the USER_SEL field.
A more flexible option to select the channel for the data to be converted to is to use the tag mode, setting the TAG
field of the
field of the
to 1. In this mode the 2 bits, DACC_CDR[13:12] which are otherwise unused, are
employed to select the channel in the same way as with the USER_SEL field. Finally, if the WORD field is set, the
2 bits, DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits, DACC_CDR[29:28] for
channel selection of the second data.
2 bits, DACC_CDR[13:12] are used for channel selection of the first data and the 2 bits, DACC_CDR[29:28] for
channel selection of the second data.