Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 1021

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The DACC Sleep Mode maximizes power saving by automatically deactivating the DACC when it is not being used for
conversions.

When a start conversion request occurs, the DACC is automatically activated. As the analog cell requires a start-up time,
the logic waits during this time and starts the conversion on the selected channel. When all conversion requests are
complete, the DACC is deactivated until the next request for conversion.

A fast wake-up mode is available in the 

 as a compromise between power saving strategy and

responsiveness. Setting the FASTW bit to 1 enables the fast wake-up mode. In fast wake-up mode the DACC is not fully
deactivated while no conversion is requested, thereby providing less power saving but faster wake-up (4 times faster).

.

This startup time differs depending of the use of the fast wake-up mode along with sleep mode, in this case the user must
set the STARTUP time corresponding to the fast wake up and not the standard startup time.

A max speed mode is available by setting the MAXS bit to 1 in the DACC_MR register. Using this mode, the DAC
Controller no longer waits to sample the end of cycle signal coming from the DACC block to start the next conversion and
uses an internal counter instead. This mode gains 2 DACC Clock periods between each consecutive conversion.

Warning: Using this mode, the EOC interrupt of the DACC_IER register should not be used as it is 2 DACC Clock
periods late.

After 

20

 

µ

s the analog voltage resulting from the converted data will start decreasing, therefore it is necessary to refresh

the channel on a regular basis to prevent this voltage loss. This is the purpose of the REFRESH field in the DACC Mode
Register where the user will define the period for the analog channels to be refreshed.

Warning: A REFRESH PERIOD field set to 0 will disable the refresh function of the DACC channels.

MCK

Write USER_SEL 

field

Selected Channel

Write DACC_CDR

DAC Channel 0

Output

DAC Channel 1

Output

EOC

Read DACC_ISR

Select Channel 0

Channel 0

Channel 1

Data 0

Data 1

Data 2

Data 0

Data 1

Data 2

Select Channel 1

None

TXRDY

CDR FIFO not full