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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
SMMLS  R4, R5, R3, R8  ; Multiplies R5 and R3, extracts top 32 bits, 
                       ; subtracts R8, truncates and writes to R4.
12.6.6.8 SMMUL
Signed Most Significant Word Multiply
Syntax
op{R}{condRdRnRm
where:
op
is one of:
SMMUL Signed Most Significant Word Multiply.
R
is a rounding error flag. If R is specified, the result is rounded instead of being
truncated. In this case the constant 0x80000000 is added to the product before
the high word is extracted.
cond
Rd
is the destination register.
Rn, Rm
are registers holding the first and second operands.
Operation
The SMMUL instruction interprets the values from Rn and Rm as two’s complement 32-bit signed integers. The SMMUL
instruction:
Multiplies the values from Rn and Rm.
Optionally rounds the result, otherwise truncates the result.
Writes the most significant signed 32 bits of the result in Rd.
Restrictions
In this instruction:
do not use SP and do not use PC.
Condition Flags
This instruction does not affect the condition code flags.
Examples
SMULL   R0, R4, R5  ; Multiplies R4 and R5, truncates top 32 bits
                    ; and writes to R0
SMULLR  R6, R2      ; Multiplies R6 and R2, rounds the top 32 bits
                    ; and writes to R6.
12.6.6.9 SMUAD and SMUSD
Signed Dual Multiply Add and Signed Dual Multiply Subtract
Syntax
op{X}{condRdRnRm
where:
op
is one of:
SMUAD Signed Dual Multiply Add.
SMUADX Signed Dual Multiply Add Reversed.
SMUSD Signed Dual Multiply Subtract.
SMUSDX Signed Dual Multiply Subtract Reversed.