Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

One dedicated pin, TST, is used to define the device operating mode. When this pin is at low level during power-up, the
device is in normal operating mode. When at high level, the device is in test mode or FFPI mode. The TST pin integrates
a permanent pull-down resistor of about 15 k

Ω,so that it can be left unconnected for normal operation. Note that when

setting the TST pin to low or high level at power up, it must remain in the same state during the duration of the whole
operation. 



SWJ-DP (Serial Wire/JTAG Debug Port)



FPB (Flash Patch Breakpoint)



DWT (Data Watchpoint and Trace)



ITM (Instrumentation Trace Macrocell)



TPIU (Trace Port Interface Unit)

The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes and
debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the Cortex-M4
technical reference manual.

The Cortex-M4 embeds a SWJ-DP Debug port which is the standard CoreSight

™

 debug port. It combines Serial Wire

Debug Port (SW-DP), from 2 to 3 pins and JTAG debug Port (JTAG-DP), 5 pins.

By default, the JTAG Debug Port is active. If the host debugger wants to switch to the Serial Wire Debug Port, it must
provide a dedicated JTAG sequence on TMS/SWDIO and TCK/SWCLK which disables JTAG-DP and enables SW-DP. 

4 watchpoints

PC sampler

data address sampler

data sampler

interrupt trace

CPU statistics

DWT

6 breakpoints

FPB

software trace

32 channels

time stamping

ITM

SWD/JTAG

SWJ-DP

SWO trace

TPIU