Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset signal
to the external components or asserted low externally to reset the microcontroller. It will reset the Core and the
peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length of the reset
pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a permanent pull-up
resistor to VDDIO of about 100 k

Ω. By default, the NRST pin is configured as an input.

The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read as
logic level 1). It integrates a pull-down resistor of about 100 k

Ω to GND, so that it can be left unconnected for normal

operations.

This pin is debounced by SCLK to improve the glitch tolerance. When the ERASE pin is tied high during less than 100
ms, it is not taken into account. The pin must be tied high during more than 220 ms to perform a Flash erase operation.

The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured as a
PIO pin. If the ERASE pin is used as a standard I/O, startup level of this pin must be low to prevent unwanted erasing.
Refer to 

. Also, if the ERASE pin is used as a

standard I/O output, asserting the pin to low does not erase the Flash.