Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
296
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 18-6. Low Power Debouncer (Push-to-Break switch, pull-down resistors)
The debouncing parameters can be adjusted and are shared (except the wake up input polarity) by both debouncers.
The number of successive identical samples to wake up the core can be configured from 2 up to 8 in the LPDBC field of
SUPC_WUMR. The period of time between 2 samples can be configured by programming the TPERIOD field in the
RTC_MR register.
The number of successive identical samples to wake up the core can be configured from 2 up to 8 in the LPDBC field of
SUPC_WUMR. The period of time between 2 samples can be configured by programming the TPERIOD field in the
RTC_MR register.
Power parameters can be adjusted by modifying the period of time in the THIGH field in RTC_MR.
The wake up polarity of the inputs can be independently configured by writing WKUPT0 and WKUPT1 fields in
SUPC_WUMR.
SUPC_WUMR.
In order to determine which wake up pin triggers the core wake up or simply which debouncer triggers an event (even if
there is no wake up, so when VDDCORE is powered on), a status flag is associated for each low power debouncer.
These 2 flags can be read in the SUPC_SR.
there is no wake up, so when VDDCORE is powered on), a status flag is associated for each low power debouncer.
These 2 flags can be read in the SUPC_SR.
A debounce event can perform an immediate clear (0 delay) on first half the general purpose backup registers (GPBR).
The LPDBCCLR bit must be set to 1 in SUPC_MR.
The LPDBCCLR bit must be set to 1 in SUPC_MR.
18.4.7.3 Clock Alarms
The RTC and the RTT alarms can generate a wake up of the core power supply. This can be enabled by writing
respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
respectively, the bits RTCEN and RTTEN to 1 in the Supply Controller Wake Up Mode Register (SUPC_WUMR).
The Supply Controller does not provide any status as the information is available in the User Interface of either the Real
Time Timer or the Real Time Clock.
Time Timer or the Real Time Clock.
18.4.7.4 Supply Monitor Detection
.
18.4.8 Low Power Tamper Detection Inputs
WKUP0 and WKUP1 can be used as tamper detect inputs.
In Backup Mode they can be used also to wake up the core. In other modes an interrupt can be generated.
If a tamper is detected, it performs an immediate clear (0 delay) on first half the general purpose backup registers
(GPBR).
(GPBR).
AT91SAM
WKUP0
WKUP1
RTCOUT0
Pull-Down
Resistors
GND
GND
GND