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SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 18-4. Wake Up Sources 
18.4.7.1 Wake Up Inputs
The wake up inputs, WKUP0 to WKUP15, can be programmed to perform a wake up of the core power supply. Each
input can be enabled by writing to 1 the corresponding bit, WKUPEN0 to WKUPEN 15, in the Wake Up Inputs Register
(SUPC_WUIR). The wake up level can be selected with the corresponding polarity bit, WKUPPL0 to WKUPPL15, also
located in SUPC_WUIR. 
All the resulting signals are wired-ORed to trigger a debounce counter, which can be programmed with the WKUPDBC
field in the Supply Controller Wake Up Mode Register (SUPC_WUMR). The WKUPDBC field can select a debouncing
period of 3, 32, 512, 4,096 or 32,768 slow clock cycles. This corresponds respectively to about 100 
μs, about 1 ms, about
16 ms, about 128 ms and about 1 second (for a typical slow clock frequency of 32 kHz). Programming WKUPDBC to 0x0
selects an immediate wake up, i.e., an enabled WKUP pin must be active according to its polarity during a minimum of
one slow clock period to wake up the core power supply.
If an enabled WKUP pin is asserted for a time longer than the debouncing period, a wake up of the core power supply is
started and the signals, WKUP0 to WKUP15 as shown in 
, are latched in the Supply Controller Status
Register (SUPC_SR). This allows the user to identify the source of the wake up, however, if a new wake up condition
occurs, the primary information is lost. No new wake up can be detected since the primary wake up condition has
disappeared.
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core 
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
WKUPT0
WKUPT1
WKUP0
WKUP1
RTTEN
rtt_alarm
Debouncer
RTCOUT0
LPDBC
Debouncer
LPDBC
RTCOUT0
LPDBCS0
LPDBCS1
LPDBCEN1
Low/High 
Level Detect
WKUPT1
LPDBCEN0
Low/High 
Level Detect
WKUPT0
Low/High 
Level Detect
Low/High 
Level Detect
Low/High 
Level Detect