Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Enhanced Embedded Flash Controller (EEFC) ensures the interface of the Flash block with the 32-bit internal bus. 

Its 128-bit or 64-bit wide memory interface increases performance. It also manages the programming, erasing, locking
and unlocking sequences of the Flash using a full set of commands. One of the commands returns the embedded Flash
descriptor definition that informs the system about the Flash organization, thus making the software generic.



Interface of the Flash Block with the 32-bit Internal Bus



Increases Performance in Thumb2 Mode with 128-bit or -64 bit Wide Memory Interface up to 100 or 120 MHz 



Code loops optimization



256 Lock Bits, Each Protecting a Lock Region 



GPNVMx General-purpose GPNVM Bits



One-by-one Lock Bit Programming-Commands Protected by a Keyword



Erases the Entire Flash



Erases by Plane



Erase by Sector



Erase by Pages



Possibility of Erasing before Programming



Locking and Unlocking Operations 



Consecutive Programming and Locking Operations



Possibility to read the Calibration Bits

The Enhanced Embedded Flash Controller (EEFC) is continuously clocked. The Power Management Controller has no
effect on its behavior.

The Enhanced Embedded Flash Controller (EEFC) interrupt line is connected to the Nested Vectored Interrupt Controller
(NVIC). Using the Enhanced Embedded Flash Controller (EEFC) interrupt requires the NVIC to be programmed first. The
EEFC interrupt is generated only on FRDY bit rising.

The embedded Flash interfaces directly with the 32-bit internal bus. The embedded Flash is composed of:



One memory plane organized in several pages of the same size.



Two 128-bit or 64-bit read buffers used for code read optimization.

EFC0

6

EFC1

7