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ATSAM4S-XPLD
311
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
20.4.2.2 Code Read Optimization
This feature is enabled if the EEFC_FMR register bit SCOD is cleared.
A system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize sequential Code Fetch.
Note:
Immediate consecutive code read accesses are not mandatory to benefit from this optimization.
The sequential code read optimization is enabled by default. If the bit SCOD in Flash Mode Register (EEFC_FMR) is set
to 1, these buffers are disabled and the sequential code read is not optimized anymore.
to 1, these buffers are disabled and the sequential code read is not optimized anymore.
Another system of 2 x 128-bit or 2 x 64-bit buffers is added in order to optimize loop code fetch (see
).
Figure 20-2. Code Read Optimization for FWS = 0
Note:
When FWS is equal to 0, all the accesses are performed in a single-cycle access.
Figure 20-3. Code Read Optimization for FWS = 3
Note:
When FWS is included between 1 and 3, in case of sequential reads, the first access takes (FWS+1) cycles, the other
ones only 1 cycle.
ones only 1 cycle.
20.4.2.3 Code Loops Optimization
The Code Loops optimization is enabled when the CLOE bit of the EEFC_FMR register is set at 1.
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15
Bytes 16-31
Bytes 32-47
Bytes 0-15
Buffer 1 (128bits)
Bytes 32-47
Bytes 0-3
Bytes 4-7
Bytes 8-11
Bytes 12-15
Bytes 16-19
Bytes 20-23
Bytes 24-27
XXX
XXX
Bytes 16-31
Byte 0
Byte 4
Byte 8
Byte 12
Byte 16
Byte 20
Byte 24
Byte 28
Byte 32
Bytes 28-31
Flash Access
Buffer 0 (128bits)
Master Clock
ARM Request
(32-bit)
Data To ARM
Buffer 1 (128bits)
0-3
XXX
XXX
Bytes 16-31
Byte 0
4
8
Bytes 0-15
Bytes 16-31
Bytes 32-47
Bytes 48-63
XXX
Bytes 0-15
4-7
8-11
12-15
12
16
20
24-27
28-31
32-35
36-39
16-19
20-23
40-43
44-47
24
28
32
36
40
44
48
52
Bytes 32-47
48-51