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ATSAM4S-XPLD
312
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
When a backward jump is inserted in the code, the pipeline of the sequential optimization is broken, and it becomes
inefficient. In this case the loop code read optimization takes over from the sequential code read optimization to avoid
insertion of wait states. The loop code read optimization is enabled by default. If in Flash Mode Register (EEFC_FMR),
the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized
anymore.
inefficient. In this case the loop code read optimization takes over from the sequential code read optimization to avoid
insertion of wait states. The loop code read optimization is enabled by default. If in Flash Mode Register (EEFC_FMR),
the bit CLOE is reset to 0 or the bit SCOD is set to 1, these buffers are disabled and the loop code read is not optimized
anymore.
When this feature is enabled, if inner loop body instructions L
0
to L
n
lay from the 128-bit flash memory cell M
b0
to the
memory cell M
p1
, after recognition of a first backward branch, the two first flash memory cells M
b0
and M
b1
targeted by
this branch are cached for fast access from the processor at the next loop iterations.
) through the loop
body with the fast read access to the loop entry cache, the whole loop can be iterated with no wait-state.
Figure 20-4. Code Loops Optimization
20.4.2.4 Data Read Optimization
The organization of the Flash in 128 bits (or 64 bits) is associated with two 128-bit (or 64-bit) prefetch buffers and one
128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store
the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads
if, for example, FWS is equal to 1 (see
128-bit (or 64-bit) data read buffer, thus providing maximum system performance. This buffer is added in order to store
the requested data plus all the data contained in the 128-bit (64-bit) aligned data. This speeds up sequential data reads
if, for example, FWS is equal to 1 (see
Flash Mode Register (EEFC_FMR) is set to 1, this buffer is disabled and the data read is not optimized anymore.
Note:
No consecutive data read accesses are mandatory to benefit from this optimization.
Figure 20-5. Data Read Optimization for FWS = 1
L
n
L
n-1
L
n-2
L
n-3
L
n-4
L
n-5
L
5
L
4
L
3
L
2
L
1
L
0
B
1
B
2
B
3
B
4
B
5
B
6
B
7
B
0
P
1
P
2
P
3
P
4
P
5
P
6
P
7
P
0
M
b0
M
b0
M
b1
M
p0
M
p1
Backward address jump
2x128-bit loop entry
cache
2x128-bit prefetch
buffer
L
0
Loop Entry instruction
L
n
Loop End instruction
Flash Memory
128-bit words
M
b0
Branch Cache 0
M
b1
Branch Cache 1
M
p0
Prefetch Buffer 0
M
p1
Prefetch Buffer 1
Flash Access
Buffer (128bits)
Master Clock
ARM Request
(32-bit)
XXX
Data To ARM
Bytes 0-15
Bytes 16-31
Bytes 0-15
Bytes 0-3
4-7
8-11
12-15
16-19
20-23
XXX
Bytes 16-31
Byte 0
4
8
12
16
20
24
28
32
36
XXX
Bytes 32-47
24-27
28-31
32-35