Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 315

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

read operations to the EEFC_FRR register are done after the last word of the descriptor has been returned, then the
EEFC_FRR register value is 0 until the next valid command.

Several commands can be used to program the Flash. 

Flash technology requires that an erase be done before programming. The full memory plane can be erased at the same
time, or several pages can be erased at the same time (refer to 

,

and the paragraph below the figure.). Also, a page erase can be automatically done before a page write using EWP or
EWPL commands.

After programming, the page (the whole lock region) can be locked to prevent miscellaneous write or erase sequences.
The lock bit can be automatically set after page programming using WPL or EWPL commands.

Data to be written are stored in an internal latch buffer. The size of the latch buffer corresponds to the page size. The
latch buffer wraps around within the internal memory area address space and is repeated as many times as the number
of pages within this address space.

Note:

Writing of 8-bit and 16-bit data is not allowed and may lead to unpredictable data corruption.

Write operations are performed in a number of wait states equal to the number of wait states for read operations.

Data are written to the latch buffer before the programming command is written to the Flash Command Register
EEFC_FCR. The sequence is as follows:



Write the full page, at any page address, within the internal memory area address space.



Programming starts as soon as the page number and the programming command are written to the Flash 
Command Register. The FRDY bit in the Flash Programming Status Register (EEFC_FSR) is automatically 
cleared.



When programming is completed, the FRDY bit in the Flash Programming Status Register (EEFC_FSR) rises. If 
an interrupt has been enabled by setting the bit FRDY in EEFC_FMR, the corresponding interrupt line of the NVIC 
is activated.

Two errors can be detected in the EEFC_FSR register after a programming sequence: 



Command Error: a bad keyword has been written in the EEFC_FCR register.



Lock Error: the page to be programmed belongs to a locked region. A command must be previously run to unlock 
the corresponding region.

FL_ID

0

Flash Interface Description

FL_SIZE

1

Flash size in bytes

FL_PAGE_SIZE

2

Page size in bytes

FL_NB_PLANE

3

Number of planes. 

FL_PLANE[0]

4

Number of bytes in the first plane.

...

FL_PLANE[FL_NB_PLANE-1]

4 + FL_NB_PLANE - 1

Number of bytes in the last plane.

FL_NB_LOCK

4 + FL_NB_PLANE

Number of lock bits. A bit is associated 
with a lock region. A lock bit is used to 
prevent write or erase operations in the 
lock region.

FL_LOCK[0]

4 + FL_NB_PLANE + 1

Number of bytes in the first lock region.

...