Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The Bus Matrix (MATRIX) implements a multi-layer AHB that enables parallel access paths between multiple AHB
masters and slaves in a system, which increases the overall bandwidth. Bus Matrix interconnects 4 AHB Masters to

 

5

AHB Slaves. The normal latency to connect a master to a slave is one cycle except for the default master of the
accessed slave which is connected directly (zero cycle latency). 

The Bus Matrix user interface also provides a Chip Configuration User Interface with Registers that allow to support
application specific features.

The Bus Matrix manages 4

 

masters, which means that each master can perform an access concurrently with others, to

an available slave.

Each master has its own decoder, which is defined specifically for each master. In order to simplify the addressing, all the
masters have the same decodings.

The Bus Matrix manages 5 slaves. Each slave has its own arbiter, allowing a different arbitration per slave.  

Master 0

Cortex-M4 Instruction/Data

Master 1

Cortex-M4 System 

Master 2

Peripheral DMA Controller (PDC)

Master 3

CRC Calculation Unit

Slave 0

Internal SRAM

Slave 1

Internal ROM

Slave 2

Internal Flash

Slave 3

External Bus Interface

Slave 4

Peripheral Bridge