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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

There are three round-robin algorithm implemented:

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Round-Robin arbitration without default master

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Round-Robin arbitration with last access master

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Round-Robin arbitration with fixed default master

This is the main algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to dispatch requests from different
masters to the same slave in a pure round-robin manner. At the end of the current access, if no other request is pending,
the slave is disconnected from all masters. This configuration incurs one latency cycle for the first access of a burst.
Arbitration without default master can be used for masters that perform significant bursts.

This is a biased round-robin algorithm used by Bus Matrix arbiters. It allows the Bus Matrix to remove the one latency
cycle for the last master that accessed the slave. In fact, at the end of the current transfer, if no other master request is
pending, the slave remains connected to the last master that performs the access. Other non privileged masters will still
get one latency cycle if they want to access the same slave. This technique can be used for masters that mainly perform
single accesses.

This is another biased round-robin algorithm, it allows the Bus Matrix arbiters to remove the one latency cycle for the
fixed default master per slave. At the end of the current access, the slave remains connected to its fixed default master.
Every request attempted by this fixed default master will not cause any latency whereas other non privileged masters will
still get one latency cycle. This technique can be used for masters that mainly perform single accesses.

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave by using
the fixed priority defined by the user. If two or more master’s requests are active at the same time, the master with the
highest priority number is serviced first. If two or more master’s requests with the same priority are active at the same
time, the master with the highest number is serviced first.

For each slave, the priority of each master may be defined through the Priority Registers for Slaves (MATRIX_PRAS and
MATRIX_PRBS).

The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in System I/O mode (such as
JTAG, ERASE, USB, etc...) or as general purpose I/O lines. Enabling or disabling the corresponding I/O lines in
peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect. However, the
direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO controller.

To prevent any single software error that may corrupt MATRIX behavior, the entire MATRIX address space from
address offset 0x000 to 0x1FC can be write-protected by setting the WPEN bit in the MATRIX Write Protect Mode
Register (MATRIX_WPMR).

If a write access to anywhere in the MATRIX address space from address offset 0x000 to 0x1FC is detected, then the
WPVS flag in the MATRIX Write Protect Status Register (MATRIX_WPSR) is set and the field WPVSRC indicates in
which register the write access has been attempted.

The WPVS flag is reset by writing the MATRIX Write Protect Mode Register (MATRIX_WPMR) with the appropriate
access key WPKEY.