Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

The External Bus Interface is designed to ensure the successful data transfer between several external devices and the
Cortex-M4 based device. The External Bus Interface of the SAM4S consists of a Static Memory Controller (SMC).

This SMC is capable of handling several types of external memory and peripheral devices, such as SRAM, PSRAM,
PROM, EPROM, EEPROM, LCD Module, NOR Flash and NAND Flash.

The Static Memory Controller (SMC) generates the signals that control the access to the external memory devices or
peripheral devices. It has 4 Chip Selects, a 24-bit address bus, and an 8-bit data bus. Separate read and write control
signals allow for direct memory and peripheral interfacing. Read and write signal waveforms are fully adjustable. 

The SMC can manage wait requests from external devices to extend the current access. The SMC is provided with an
automatic slow clock mode. In slow clock mode, it switches from user-programmed waveforms to slow-rate specific
waveforms on read and write signals. The SMC supports asynchronous burst read in page mode access for page size up
to 32 bytes.

The External Data Bus can be scrambled/unscrambled by means of user keys.

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16-Mbyte Address Space per Chip Select

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8- bit Data Bus

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Word, Halfword, Byte Transfers

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Byte Write or Byte Select Lines

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Programmable Setup, Pulse And Hold Time for Read Signals per Chip Select

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Programmable Setup, Pulse And Hold Time for Write Signals per Chip Select

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Programmable Data Float Time per Chip Select

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Compliant with LCD Module

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External Wait Request

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Automatic Switch to Slow Clock Mode

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Asynchronous Read in Page Mode Supported: Page Size Ranges from 4 to 32 Bytes

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NAND Flash additional logic supporting NAND Flash with Multiplexed Data/Address buses

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Hardware Configurable number of chip select from 1 to 4

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Programmable timing on a per chip select basis