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ATSAM4S-XPLD
391
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-1. Memory Connections for Four External Devices
26.6
Connection to External Devices
26.6.1 Data Bus Width
The data bus width is 8 bits.
Figure 26-2. Memory Connection for an 8-bit Data Bus
26.6.1.1 NAND Flash Support
The SMC integrates circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller. It depends on the programming of the SMC_NFCSx
field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface. For details on this register, refer to the Bus
Matrix User Interface section. Access to an external NAND Flash device via the address space reserved to the chip
select programmed.
field in the CCFG_SMCNFCS Register on the Bus Matrix User Interface. For details on this register, refer to the Bus
Matrix User Interface section. Access to an external NAND Flash device via the address space reserved to the chip
select programmed.
The user can connect up to 4 NAND Flash devices with separated chip select.
The NAND Flash logic drives the read and write command signals of the SMC on the NANDOE and NANDWE signals
when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address fails to lie
in the NCSx programmed address space.
when the NCSx programmed is active. NANDOE and NANDWE are disabled as soon as the transfer address fails to lie
in the NCSx programmed address space.
NRD
NWE
A[23:0]
D[7:0]
8
Memory Enable
Memory Enable
Memory Enable
Memory Enable
Output Enable
Write Enable
A[23:0]
D[7:0]
NCS3
NCS0
NCS1
NCS2
NCS[0] - NCS[3]
SMC
24
SMC
NWE
NRD
NCS[0]
Write Enable
Output Enable
Memory Enable
D[7:0]
D[7:0]
A[18:0]
A[18:0]