Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos

 400

SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

All NWE and NCS (write) timings are defined separately for each chip select as an integer number of Master Clock
cycles. To ensure that the NWE and NCS timings are coherent, the user must define the total write cycle instead of the
hold timing. This implicitly defines the NWE hold time and NCS (write) hold times as:

NWE_HOLD = NWE_CYCLE - NWE_SETUP - NWE_PULSE 

NCS_WR_HOLD = NWE_CYCLE - NCS_WR_SETUP - NCS_WR_PULSE

If null setup parameters are programmed for NWE and/or NCS, NWE and/or NCS remain active continuously in case of
consecutive write cycles in the same memory (see 

). However, for devices that perform write operations on

the rising edge of NWE or NCS, such as SRAM, either a setup or a hold must be programmed.

Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.

The WRITE_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal
controls the write operation. 

 shows the waveforms of a write operation with WRITE_MODE set to 1. The data is put on the bus during

the pulse and hold steps of the NWE signal. The internal data buffers are switched to output mode after the
NWE_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NCS.

NCS

MCK

NWE 

D[7:0]

NWE_PULSE

NCS_WR_PULSE

NWE_CYCLE

NWE_PULSE

NCS_WR_PULSE

NWE_CYCLE

NWE_PULSE

NCS_WR_PULSE

NWE_CYCLE

A[23:0]