Atmel SAM4S-XPLD Atmel ATSAM4S-XPLD ATSAM4S-XPLD Hoja De Datos
Los códigos de productos
ATSAM4S-XPLD
401
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
Figure 26-11.WRITE_MODE = 1. The write operation is controlled by NWE
26.8.4.2 Write is Controlled by NCS (WRITE_MODE = 0)
shows the waveforms of a write operation with WRITE_MODE set to 0. The data is put on the bus during
the pulse and hold steps of the NCS signal. The internal data buffers are switched to output mode after the
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
NCS_WR_SETUP time, and until the end of the write cycle, regardless of the programmed waveform on NWE.
Figure 26-12.WRITE_MODE = 0. The write operation is controlled by NCS
26.8.5 Write Protected Registers
To prevent any single software error that may corrupt SMC behavior, the registers listed below can be write-protected by
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
setting the WPEN bit in the SMC Write Protect Mode Register (SMC_WPMR).
If a write access in a write-protected register is detected, then the WPVS flag in the SMC Write Protect Status Register
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
(SMC_WPSR) is set and the field WPVSRC indicates in which register the write access has been attempted.
The WPVS flag is automatically reset after reading the SMC Write Protect Status Register (SMC_WPSR).
List of the write-protected registers:
MCK
D[7:0]
NCS
A[23:0]
NWE
MCK
D[7:0]
NCS
NWE
A[23:0]